Update the ihfc driver with a patch from the author. He writes: This patch
enables the driver to work on current (I have not tested the isa part fully, but I suppose it should work). The patching from jlemon caused a crash at probe time. This is probably my fault not having added a comment for "RESET_SOFT" saying: "this resets all!". Submitted by: Hans Petter Selasky <hselasky@c2i.net>
This commit is contained in:
Hellmuth Michaelis
parent
5ed4160254
commit
2fd9d69993
@ -31,12 +31,7 @@
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*
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* $FreeBSD$
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*
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* last edit-date: [Thu Oct 26 08:29:06 2000]
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*
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* NOTE:
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* - October 19th: made minor changes to HDLC_ENCODE macro
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* Please conform "ihfc/i4b_ihfc_drv.c" (ihfc_hdlc_Bwrite)
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* for correct usage! (-hp)
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* last edit-date: [Wed Jul 19 09:41:13 2000]
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*
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*---------------------------------------------------------------------------*/
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@ -95,7 +90,7 @@ const u_short HDLC_FCS_TAB[256] = { 0x0000,
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*
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* bits[4..7]: Special bytes like 0x7e, 0x7d, 0xfd ... are flagged here
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* NOTE: Special bytes also means 'abort' bytes (7 or more
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* continious set bits)
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* continuous set bits)
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*
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* bits[8..11]: A copy of bits[0..3] but only incremented by one.
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* NOTE: 0x7e has value '8' instead of '0'. Internal reasons.
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@ -149,7 +144,7 @@ const u_short HDLC_BIT_TAB[256] = { 0x0100,
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*
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* next: 'continue' or 'goto xxx'
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*
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* cfr: complet frame
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* cfr: complete frame
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* nfr: new frame
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* NOTE: must setup 'len' and 'dst', so that 'dst' may be written
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* at most 'len' times.
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@ -165,7 +160,7 @@ const u_short HDLC_BIT_TAB[256] = { 0x0100,
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* NOTE: these variables have to be 'suspended' / 'resumed' somehow:
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* flag, blevel, crc, ib, tmp, len
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* NOTE: zero is default value for all variables.
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* NOTE: each time 'dst' is written, 'len' is decremented by one.
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* NOTE: each time 'dst' is written, 'len' is decreased by one.
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*---------------------------------------------------------------------------*/
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#define HDLC_DECODE(dst, len, tmp, tmp2, blevel, ib, crc, flag, rddcmd, nfrcmd, \
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@ -280,20 +275,21 @@ const u_short HDLC_BIT_TAB[256] = { 0x0100,
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* u_short: tmp2, blevel, ib, crc, len
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* u_int: tmp
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*
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* gfr: get new frame, free old, and exit if no frame
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* NOTE: must setup 'len' and 'src', so that 'src' can be read
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* 'len' times.
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* gfr: This is the place where you free the last [mbuf] chain, and get
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* the next one. If a mbuf is available the code should setup 'len'
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* and 'src' so that 'src' may be read 'len' times. If no mbuf is
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* available leave 'len' and 'src' untouched.
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*
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* wrd: write data (output = (u_char)tmp)
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*
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* d: dummy
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*
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* NOTE: setting flag to '-1' and len to '0' => abort byte will be sent
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* NOTE: setting flag to '-2' and len to '0' => abort bytes will be sent
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* NOTE: these variables have to be 'suspended' / 'resumed' somehow:
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* flag, blevel, crc, ib, tmp, len
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* NOTE: zero is default value for all variables.
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* NOTE: each time 'src' is read, 'len' is decremented by one.
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* NOTE: gfr must setup 'len'.
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* NOTE: each time 'src' is read, 'len' is decreased by one.
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* NOTE: neither cmd's should exit through 'goto' or 'break' statements.
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*---------------------------------------------------------------------------*/
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#define HDLC_ENCODE(src, len, tmp, tmp2, blevel, ib, crc, flag, gfrcmd, wrdcmd, d) \
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@ -305,7 +301,7 @@ const u_short HDLC_BIT_TAB[256] = { 0x0100,
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len++; \
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\
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switch(++flag) \
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{ case 0: /* abort */ \
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{ default: /* abort */ \
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tmp = blevel = 0; /* zero is default */ \
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tmp2 = 0xff; \
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goto j3##d; \
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@ -313,8 +309,8 @@ const u_short HDLC_BIT_TAB[256] = { 0x0100,
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case 2: /* 2nd time FS */ \
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tmp2 = 0x7e; \
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goto j3##d; \
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case 3: /* get new frame */ \
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gfrcmd; \
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case 3: \
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gfrcmd; /* get new frame */ \
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if (!len--) \
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{ \
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len++; \
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@ -328,15 +324,14 @@ const u_short HDLC_BIT_TAB[256] = { 0x0100,
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ib = 0; \
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goto j1##d; /* first byte */ \
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} \
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case 4: /* CRC (lsb's) */ \
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crc ^= -1; \
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tmp2 = (u_char)crc; \
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crc >>= 8; \
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goto j2##d; \
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case 5: /* CRC (msb's) */ \
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tmp2 = (u_char)crc; \
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case 4: \
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crc ^= -1; \
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tmp2 = (u_char)crc; \
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goto j2##d; /* CRC (lsb's) */ \
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case 5: \
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tmp2 = (u_char)(crc >> 8); \
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flag = 1; \
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goto j2##d; /* CRC stuff */ \
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goto j2##d; /* CRC (msb's) */ \
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} \
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} \
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else \
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@ -395,3 +390,4 @@ const u_short HDLC_BIT_TAB[256] = { 0x0100,
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#endif /* _I4B_HDLC_H_ */
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@ -323,6 +323,9 @@ ihfc_control(ihfc_sc_t *sc, int flag)
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S_SQXR |= 0x40; /* power down */
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S_INT_M2 &= ~0x01;
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S_MASK |= 0x02;
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S_SPCR &= ~0x0f; /* send 1's only */
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S_SCTRL &= ~0x83; /* send 1's only + enable oscillator */
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@ -351,14 +354,14 @@ ihfc_init (ihfc_sc_t *sc, u_char chan, int prot, int activate)
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do
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{ if (chan < 2) /* D-Channel */
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{
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S_IFQUEUE.ifq_maxlen = IFQ_MAXLEN;
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mtx_init(&S_IFQUEUE.ifq_mtx, "i4b_ihfc", MTX_DEF);
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i4b_Dfreembuf(S_MBUF);
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i4b_Dcleanifq(&S_IFQUEUE);
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if (!IF_QEMPTY(&S_IFQUEUE)) i4b_Dcleanifq(&S_IFQUEUE);
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RESET_SOFT_CHAN(sc, chan);
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S_IFQUEUE.ifq_maxlen = IFQ_MAXLEN;
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mtx_init(&S_IFQUEUE.ifq_mtx, "i4b_ihfc", MTX_DEF);
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if (!activate) continue;
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if (S_HFC & HFC_1)
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@ -374,14 +377,14 @@ ihfc_init (ihfc_sc_t *sc, u_char chan, int prot, int activate)
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}
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else /* B-Channel */
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{
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S_IFQUEUE.ifq_maxlen = IFQ_MAXLEN;
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mtx_init(&S_IFQUEUE.ifq_mtx, "i4b_ihfc", MTX_DEF);
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i4b_Bfreembuf(S_MBUF);
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i4b_Bcleanifq(&S_IFQUEUE);
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if (!IF_QEMPTY(&S_IFQUEUE)) i4b_Bcleanifq(&S_IFQUEUE);
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RESET_SOFT_CHAN(sc, chan);
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S_IFQUEUE.ifq_maxlen = IFQ_MAXLEN;
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mtx_init(&S_IFQUEUE.ifq_mtx, "i4b_ihfc", MTX_DEF);
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S_PROT = prot;
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if (!activate) continue;
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@ -711,6 +714,10 @@ ihfc_intr1 (ihfc_sc_t *sc)
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{
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if (chan == 1) break;
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if (S_FILTER) S_FILTER(sc, chan);
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HFC_END;
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DELAY(10);
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HFC_BEG;
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}
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}
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@ -766,6 +773,10 @@ ihfc_intr2 (ihfc_sc_t *sc)
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{
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if (chan == 1) continue;
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if (S_FILTER) S_FILTER(sc, chan);
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HFC_END;
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DELAY(10);
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HFC_BEG;
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}
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}
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@ -1408,7 +1419,7 @@ ihfc_hdlc_Bwrite (ihfc_sc_t *sc, u_char chan)
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{
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/* XDU */
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flag = -1;
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flag = -2;
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len = 0;
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NDBGL1(L1_S_ERR, "XDU (unit=%d)", S_UNIT);
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@ -1588,7 +1599,7 @@ ihfc_test_Bwrite (ihfc_sc_t *sc, u_char chan)
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j0:
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sendlen = (u_short)ihfc_Bsel_fifo(sc, chan, 0);
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sendlen = /* (u_short)ihfc_Bsel_fifo(sc, chan, 0); */ 0;
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if (sendlen == 0x5ff) printf("(send empty)");
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@ -1649,7 +1660,7 @@ ihfc_test_Bread (ihfc_sc_t *sc, u_char chan)
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if (S_UNIT != 0) return;
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reclen = (u_short)ihfc_Bsel_fifo(sc, chan, 0);
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reclen = /* (u_short)ihfc_Bsel_fifo(sc, chan, 0); */ 0;
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S_BYTES += reclen;
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@ -136,7 +136,10 @@ ihfc_ph_data_req(int unit, struct mbuf *m, int freeflag)
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else
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{
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NDBGL1(L1_ERROR, "No frame out (unit = %d)", unit);
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i4b_Dfreembuf(m);
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if (m) i4b_Dfreembuf(m);
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HFC_END;
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return 0;
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}
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if (S_INTR_ACTIVE) S_INT_S1 |= 0x04;
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@ -28,7 +28,7 @@
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* -------------------------------------------------
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*
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* - Everything which has got anything to to with "PnP" bus setup has
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* been put here.
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* been put here, except the chip spesific "PnP" setup.
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*
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*
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* last edit-date: [Wed Jul 19 09:41:07 2000]
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@ -91,9 +91,9 @@ const struct ihfc_pnp_ids
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}
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ihfc_pnp_ids[] =
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{
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{ 0x10262750, FLAG_TELES_S0_163C, HFC_S , 2, 0x200 , 0xd},
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{ 0x20262750, FLAG_TELES_S0_163C, HFC_SP, 0, 0x000 , 0xf},
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{ 0x1411d805, FLAG_ACER_P10 , HFC_S , 1, 0x300 , 0xe},
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{ 0x10262750, FLAG_TELES_S0_163C, HFC_S , 2, 0x200 , 0x2d},
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{ 0x20262750, FLAG_TELES_S0_163C, HFC_SP, 0, 0x000 , 0x0f},
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{ 0x1411d805, FLAG_ACER_P10 , HFC_S , 1, 0x300 , 0x0e},
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{ 0 }
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};
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@ -149,6 +149,8 @@ ihfc_pnp_probe(device_t dev)
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u_int32_t vid = isa_get_vendorid(dev); /* vendor id */
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ihfc_id_t *ids = &ihfc_pnp_ids[0]; /* ids ptr */
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ihfc_sc_t *sc = &ihfc_softc[unit]; /* softc */
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u_char flag = 0; /* flag */
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void *dummy = 0; /* a dummy */
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HFC_VAR;
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@ -161,12 +163,18 @@ ihfc_pnp_probe(device_t dev)
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if (!vid) return ihfc_isa_probe(dev);
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HFC_BEG;
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for ( ;(ids->vid); ids++)
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{
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if (ids->vid == vid)
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{
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bzero(sc, sizeof(ihfc_sc_t)); /* reset data structure */
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flag = 0;
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bzero(sc, sizeof(ihfc_sc_t)); /* reset data structure.*
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* Zero is default for *
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* most, so calling the *
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* int. handler now will*
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* not be a problem. */
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S_IOBASE[0] = bus_alloc_resource(
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dev, SYS_RES_IOPORT, &S_IORID[0],
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@ -201,6 +209,14 @@ ihfc_pnp_probe(device_t dev)
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S_IIRQ = IIRQ3[rman_get_start(S_IRQ) & 0xf];
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}
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/* setup interrupt routine now to avvoid stray *
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* interrupts. */
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bus_setup_intr(dev, S_IRQ, INTR_TYPE_NET, (void(*)(void*))
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HFC_INTR, sc, &dummy);
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flag = 1;
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if (!HFC_CONTROL(sc, 1))
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{
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HFC_END;
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@ -214,7 +230,7 @@ ihfc_pnp_probe(device_t dev)
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}
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}
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ihfc_pnp_detach(dev, 0);
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ihfc_pnp_detach(dev, flag);
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}
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}
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@ -232,6 +248,8 @@ ihfc_isa_probe(device_t dev)
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ihfc_sc_t *sc = &ihfc_softc[unit]; /* softc */
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const u_char *irq = &IRQ0[0]; /* irq's to try */
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const u_long *iobase = &IO0[0]; /* iobases to try */
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u_char flag = 0; /* flag */
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void *dummy = 0; /* a dummy */
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HFC_VAR;
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@ -266,6 +284,8 @@ ihfc_isa_probe(device_t dev)
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iobase++;
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}
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flag = 0;
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if (*irq && *iobase) /* we got our resources, now test chip */
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{
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S_DLP = IHFC_DLP; /* set D-priority */
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@ -281,6 +301,14 @@ ihfc_isa_probe(device_t dev)
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S_IIRQ = IIRQ0[*irq]; /* set internal irq */
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S_IIO = *iobase; /* set internal iobase */
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/* setup interrupt routine now to avvoid stray *
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* interrupts. */
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bus_setup_intr(dev, S_IRQ, INTR_TYPE_NET, (void(*)(void*))
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HFC_INTR, sc, &dummy);
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flag = 1;
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if (!HFC_CONTROL(sc, 1))
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{
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device_set_desc(dev, "TELEINT ISDN SPEED No. 1");
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@ -290,7 +318,7 @@ ihfc_isa_probe(device_t dev)
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}
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}
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ihfc_pnp_detach(dev, 0);
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ihfc_pnp_detach(dev, flag);
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if (*irq && *++iobase) goto j0; /* try again */
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@ -310,7 +338,6 @@ ihfc_pnp_attach(device_t dev)
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{
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u_int unit = device_get_unit(dev); /* get unit */
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ihfc_sc_t *sc = &ihfc_softc[unit]; /* softc */
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void *dummy = 0; /* a dummy */
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HFC_VAR;
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HFC_BEG;
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@ -324,9 +351,6 @@ ihfc_pnp_attach(device_t dev)
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HFC_INIT(sc, 2, 0, 0); /* Init B1 - Channel */
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HFC_INIT(sc, 4, 0, 0); /* Init B2 - Channel */
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bus_setup_intr(dev, S_IRQ, INTR_TYPE_NET, (void(*)(void*))
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HFC_INTR, sc, &dummy);
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HFC_END;
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return 0; /* success */
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