AGP GART driver for NVIDIA nForce/nForce2 chipsets.
This commit is contained in:
Matthew N. Dodd
parent
afe1c7ba84
commit
34345c0870
@ -393,3 +393,4 @@ pci/agp_sis.c optional agp
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pci/agp_ali.c optional agp
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pci/agp_amd.c optional agp
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pci/agp_i810.c optional agp
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pci/agp_nvidia.c optional agp
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453
sys/dev/agp/agp_nvidia.c
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453
sys/dev/agp/agp_nvidia.c
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@ -0,0 +1,453 @@
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/*-
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* Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Written using information gleaned from the
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* NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
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*/
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#include "opt_bus.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#if __FreeBSD_version < 500000
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#include "opt_pci.h"
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#endif
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#if __FreeBSD_version > 500000
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#include <sys/lockmgr.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#endif
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <pci/agppriv.h>
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#include <pci/agpreg.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#define NVIDIA_VENDORID 0x10de
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#define NVIDIA_DEVICEID_NFORCE 0x01a4
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#define NVIDIA_DEVICEID_NFORCE2 0x01e0
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struct agp_nvidia_softc {
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struct agp_softc agp;
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u_int32_t initial_aperture; /* aperture size at startup */
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struct agp_gatt * gatt;
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device_t dev; /* AGP Controller */
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device_t mc1_dev; /* Memory Controller */
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device_t mc2_dev; /* Memory Controller */
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device_t bdev; /* Bridge */
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u_int32_t wbc_mask;
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int num_dirs;
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int num_active_entries;
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off_t pg_offset;
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};
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static const char * agp_nvidia_match (device_t dev);
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static int agp_nvidia_probe (device_t);
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static int agp_nvidia_attach (device_t);
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static int agp_nvidia_detach (device_t);
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static u_int32_t agp_nvidia_get_aperture (device_t);
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static int agp_nvidia_set_aperture (device_t, u_int32_t);
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static int agp_nvidia_bind_page (device_t, int, vm_offset_t);
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static int agp_nvidia_unbind_page (device_t, int);
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static int nvidia_init_iorr (u_int32_t, u_int32_t);
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static const char *
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agp_nvidia_match (device_t dev)
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{
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if (pci_get_class(dev) != PCIC_BRIDGE ||
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pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
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pci_get_vendor(dev) != NVIDIA_VENDORID)
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return (NULL);
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switch (pci_get_device(dev)) {
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case NVIDIA_DEVICEID_NFORCE:
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return ("NVIDIA nForce AGP Controller");
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case NVIDIA_DEVICEID_NFORCE2:
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return ("NVIDIA nForce2 AGP Controller");
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}
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return ("NVIDIA Generic AGP Controller");
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}
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static int
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agp_nvidia_probe (device_t dev)
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{
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const char *desc;
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desc = agp_nvidia_match(dev);
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if (desc) {
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device_verbose(dev);
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device_set_desc(dev, desc);
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return (0);
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}
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return (ENXIO);
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}
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static int
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agp_nvidia_attach (device_t dev)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt;
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u_int32_t apbase;
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u_int32_t aplimit;
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u_int32_t temp;
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int size;
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int i;
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int error;
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switch (pci_get_device(dev)) {
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case NVIDIA_DEVICEID_NFORCE:
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sc->wbc_mask = 0x00010000;
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break;
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case NVIDIA_DEVICEID_NFORCE2:
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sc->wbc_mask = 0x80000000;
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break;
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default:
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sc->wbc_mask = 0;
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break;
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}
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/* AGP Controller */
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sc->dev = dev;
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/* Memory Controller 1 */
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sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
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if (sc->mc1_dev == NULL) {
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device_printf(dev,
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"Unable to find NVIDIA Memory Controller 1.\n");
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return (ENODEV);
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}
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/* Memory Controller 2 */
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sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
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if (sc->mc2_dev == NULL) {
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device_printf(dev,
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"Unable to find NVIDIA Memory Controller 2.\n");
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return (ENODEV);
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}
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/* AGP Host to PCI Bridge */
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sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
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if (sc->bdev == NULL) {
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device_printf(dev,
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"Unable to find NVIDIA AGP Host to PCI Bridge.\n");
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return (ENODEV);
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}
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error = agp_generic_attach(dev);
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if (error)
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return (error);
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sc->initial_aperture = AGP_GET_APERTURE(dev);
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for (;;) {
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gatt = agp_alloc_gatt(dev);
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if (gatt)
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break;
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/*
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* Probably contigmalloc failure. Try reducing the
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* aperture so that the gatt size reduces.
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*/
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if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
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goto fail;
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}
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sc->gatt = gatt;
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apbase = rman_get_start(sc->agp.as_aperture);
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aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
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pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
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pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
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error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
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if (error) {
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device_printf(dev, "Failed to setup IORRs\n");
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goto fail;
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}
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/* directory size is 64k */
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size = AGP_GET_APERTURE(dev) / 1024 / 1024;
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sc->num_dirs = size / 64;
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sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
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sc->pg_offset = 0;
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if (sc->num_dirs == 0) {
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sc->num_dirs = 1;
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sc->num_active_entries /= (64 / size);
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sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
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~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
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}
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/* (G)ATT Base Address */
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for (i = 0; i < 8; i++) {
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
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(sc->gatt->ag_physical +
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(i % sc->num_dirs) * 64 * 1024),
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4);
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}
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/* GTLB Control */
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temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
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/* GART Control */
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temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
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pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
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return (0);
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fail:
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agp_generic_detach(dev);
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return (ENOMEM);
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}
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static int
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agp_nvidia_detach (device_t dev)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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int error;
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u_int32_t temp;
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error = agp_generic_detach(dev);
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if (error)
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return (error);
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/* GART Control */
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temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
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pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
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/* GTLB Control */
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temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
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/* Put the aperture back the way it started. */
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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/* restore iorr for previous aperture size */
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nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
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sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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return (0);
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}
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static u_int32_t
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agp_nvidia_get_aperture(device_t dev)
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{
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u_int8_t key;
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key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
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return (1 << (24 + (key ? key : 5)));
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}
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static int
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agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
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{
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u_int8_t val;
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u_int8_t key;
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switch (aperture) {
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case (512 * 1024 * 1024): key = 0; break;
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case (256 * 1024 * 1024): key = 8; break;
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case (128 * 1024 * 1024): key = 12; break;
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case (64 * 1024 * 1024): key = 14; break;
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case (32 * 1024 * 1024): key = 15; break;
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default:
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device_printf(dev, "Invalid aperture size (%dMb)\n",
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aperture / 1024 / 1024);
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return (EINVAL);
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}
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val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
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pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
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return (0);
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}
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static int
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agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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u_int32_t index;
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return (EINVAL);
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index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
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sc->gatt->ag_virtual[index] = physical;
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return (0);
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}
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static int
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agp_nvidia_unbind_page(device_t dev, int offset)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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u_int32_t index;
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return (EINVAL);
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index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
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sc->gatt->ag_virtual[index] = 0;
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return (0);
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}
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static int
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agp_nvidia_flush_tlb (device_t dev, int offset)
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{
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struct agp_nvidia_softc *sc;
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u_int32_t wbc_reg, temp;
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int i;
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sc = (struct agp_nvidia_softc *)device_get_softc(dev);
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if (sc->wbc_mask) {
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wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
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wbc_reg |= sc->wbc_mask;
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pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
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/* Wait no more than 3 seconds. */
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for (i = 0; i < 3000; i++) {
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wbc_reg = pci_read_config(sc->mc1_dev,
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AGP_NVIDIA_1_WBC, 4);
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if ((sc->wbc_mask & wbc_reg) == 0)
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break;
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else
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DELAY(1000);
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}
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if (i == 3000)
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device_printf(dev,
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"TLB flush took more than 3 seconds.\n");
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}
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/* Flush TLB entries. */
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for(i = 0; i < 32 + 1; i++)
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temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
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for(i = 0; i < 32 + 1; i++)
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temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
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return (0);
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}
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#define SYSCFG 0xC0010010
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#define IORR_BASE0 0xC0010016
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#define IORR_MASK0 0xC0010017
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#define AMD_K7_NUM_IORR 2
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static int
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nvidia_init_iorr(u_int32_t addr, u_int32_t size)
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{
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quad_t base, mask, sys;
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u_int32_t iorr_addr, free_iorr_addr;
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/* Find the iorr that is already used for the addr */
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/* If not found, determine the uppermost available iorr */
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free_iorr_addr = AMD_K7_NUM_IORR;
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for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
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base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
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mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
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if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
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break;
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if ((mask & 0x00000800ULL) == 0)
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free_iorr_addr = iorr_addr;
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}
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if (iorr_addr >= AMD_K7_NUM_IORR) {
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iorr_addr = free_iorr_addr;
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if (iorr_addr >= AMD_K7_NUM_IORR)
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return (EINVAL);
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}
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base = (addr & ~0xfff) | 0x18;
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mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
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wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
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wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
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sys = rdmsr(SYSCFG);
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sys |= 0x00100000ULL;
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wrmsr(SYSCFG, sys);
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return (0);
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}
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static device_method_t agp_nvidia_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, agp_nvidia_probe),
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DEVMETHOD(device_attach, agp_nvidia_attach),
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DEVMETHOD(device_detach, agp_nvidia_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* AGP interface */
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DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
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DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
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DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
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DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
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DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
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DEVMETHOD(agp_enable, agp_generic_enable),
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DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
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DEVMETHOD(agp_free_memory, agp_generic_free_memory),
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DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
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DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t agp_nvidia_driver = {
|
||||
"agp",
|
||||
agp_nvidia_methods,
|
||||
sizeof(struct agp_nvidia_softc),
|
||||
};
|
||||
|
||||
static devclass_t agp_devclass;
|
||||
|
||||
DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
|
||||
MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
|
||||
MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
|
||||
@ -202,4 +202,17 @@
|
||||
#define AGP_I852_GME 0x2
|
||||
#define AGP_I852_GM 0x5
|
||||
|
||||
/*
|
||||
* NVIDIA nForce/nForce2 registers
|
||||
*/
|
||||
#define AGP_NVIDIA_0_APBASE 0x10
|
||||
#define AGP_NVIDIA_0_APSIZE 0x80
|
||||
#define AGP_NVIDIA_1_WBC 0xf0
|
||||
#define AGP_NVIDIA_2_GARTCTRL 0xd0
|
||||
#define AGP_NVIDIA_2_APBASE 0xd8
|
||||
#define AGP_NVIDIA_2_APLIMIT 0xdc
|
||||
#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
|
||||
#define AGP_NVIDIA_3_APBASE 0x50
|
||||
#define AGP_NVIDIA_3_APLIMIT 0x54
|
||||
|
||||
#endif /* !_PCI_AGPREG_H_ */
|
||||
|
||||
@ -5,7 +5,8 @@
|
||||
KMOD= agp
|
||||
SRCS= agp.c agp_if.c
|
||||
.if ${MACHINE_ARCH} == "i386"
|
||||
SRCS+= agp_i810.c agp_intel.c agp_via.c agp_sis.c agp_ali.c agp_amd.c
|
||||
SRCS+= agp_i810.c agp_intel.c agp_via.c agp_sis.c agp_ali.c agp_amd.c \
|
||||
agp_nvidia.c
|
||||
.endif
|
||||
.if ${MACHINE_ARCH} == "alpha"
|
||||
SRCS+= agp_amd.c
|
||||
|
||||
453
sys/pci/agp_nvidia.c
Normal file
453
sys/pci/agp_nvidia.c
Normal file
@ -0,0 +1,453 @@
|
||||
/*-
|
||||
* Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Written using information gleaned from the
|
||||
* NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
|
||||
*/
|
||||
|
||||
#include "opt_bus.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/lock.h>
|
||||
|
||||
#if __FreeBSD_version < 500000
|
||||
#include "opt_pci.h"
|
||||
#endif
|
||||
|
||||
#if __FreeBSD_version > 500000
|
||||
#include <sys/lockmgr.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/proc.h>
|
||||
#endif
|
||||
|
||||
#include <pci/pcivar.h>
|
||||
#include <pci/pcireg.h>
|
||||
#include <pci/agppriv.h>
|
||||
#include <pci/agpreg.h>
|
||||
|
||||
#include <vm/vm.h>
|
||||
#include <vm/vm_object.h>
|
||||
#include <vm/pmap.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/rman.h>
|
||||
|
||||
#define NVIDIA_VENDORID 0x10de
|
||||
#define NVIDIA_DEVICEID_NFORCE 0x01a4
|
||||
#define NVIDIA_DEVICEID_NFORCE2 0x01e0
|
||||
|
||||
struct agp_nvidia_softc {
|
||||
struct agp_softc agp;
|
||||
u_int32_t initial_aperture; /* aperture size at startup */
|
||||
struct agp_gatt * gatt;
|
||||
|
||||
device_t dev; /* AGP Controller */
|
||||
device_t mc1_dev; /* Memory Controller */
|
||||
device_t mc2_dev; /* Memory Controller */
|
||||
device_t bdev; /* Bridge */
|
||||
|
||||
u_int32_t wbc_mask;
|
||||
int num_dirs;
|
||||
int num_active_entries;
|
||||
off_t pg_offset;
|
||||
};
|
||||
|
||||
static const char * agp_nvidia_match (device_t dev);
|
||||
static int agp_nvidia_probe (device_t);
|
||||
static int agp_nvidia_attach (device_t);
|
||||
static int agp_nvidia_detach (device_t);
|
||||
static u_int32_t agp_nvidia_get_aperture (device_t);
|
||||
static int agp_nvidia_set_aperture (device_t, u_int32_t);
|
||||
static int agp_nvidia_bind_page (device_t, int, vm_offset_t);
|
||||
static int agp_nvidia_unbind_page (device_t, int);
|
||||
|
||||
static int nvidia_init_iorr (u_int32_t, u_int32_t);
|
||||
|
||||
static const char *
|
||||
agp_nvidia_match (device_t dev)
|
||||
{
|
||||
if (pci_get_class(dev) != PCIC_BRIDGE ||
|
||||
pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
|
||||
pci_get_vendor(dev) != NVIDIA_VENDORID)
|
||||
return (NULL);
|
||||
|
||||
switch (pci_get_device(dev)) {
|
||||
case NVIDIA_DEVICEID_NFORCE:
|
||||
return ("NVIDIA nForce AGP Controller");
|
||||
case NVIDIA_DEVICEID_NFORCE2:
|
||||
return ("NVIDIA nForce2 AGP Controller");
|
||||
}
|
||||
return ("NVIDIA Generic AGP Controller");
|
||||
}
|
||||
|
||||
static int
|
||||
agp_nvidia_probe (device_t dev)
|
||||
{
|
||||
const char *desc;
|
||||
|
||||
desc = agp_nvidia_match(dev);
|
||||
if (desc) {
|
||||
device_verbose(dev);
|
||||
device_set_desc(dev, desc);
|
||||
return (0);
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_nvidia_attach (device_t dev)
|
||||
{
|
||||
struct agp_nvidia_softc *sc = device_get_softc(dev);
|
||||
struct agp_gatt *gatt;
|
||||
u_int32_t apbase;
|
||||
u_int32_t aplimit;
|
||||
u_int32_t temp;
|
||||
int size;
|
||||
int i;
|
||||
int error;
|
||||
|
||||
switch (pci_get_device(dev)) {
|
||||
case NVIDIA_DEVICEID_NFORCE:
|
||||
sc->wbc_mask = 0x00010000;
|
||||
break;
|
||||
case NVIDIA_DEVICEID_NFORCE2:
|
||||
sc->wbc_mask = 0x80000000;
|
||||
break;
|
||||
default:
|
||||
sc->wbc_mask = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* AGP Controller */
|
||||
sc->dev = dev;
|
||||
|
||||
/* Memory Controller 1 */
|
||||
sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
|
||||
if (sc->mc1_dev == NULL) {
|
||||
device_printf(dev,
|
||||
"Unable to find NVIDIA Memory Controller 1.\n");
|
||||
return (ENODEV);
|
||||
}
|
||||
|
||||
/* Memory Controller 2 */
|
||||
sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
|
||||
if (sc->mc2_dev == NULL) {
|
||||
device_printf(dev,
|
||||
"Unable to find NVIDIA Memory Controller 2.\n");
|
||||
return (ENODEV);
|
||||
}
|
||||
|
||||
/* AGP Host to PCI Bridge */
|
||||
sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
|
||||
if (sc->bdev == NULL) {
|
||||
device_printf(dev,
|
||||
"Unable to find NVIDIA AGP Host to PCI Bridge.\n");
|
||||
return (ENODEV);
|
||||
}
|
||||
|
||||
error = agp_generic_attach(dev);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
sc->initial_aperture = AGP_GET_APERTURE(dev);
|
||||
|
||||
for (;;) {
|
||||
gatt = agp_alloc_gatt(dev);
|
||||
if (gatt)
|
||||
break;
|
||||
/*
|
||||
* Probably contigmalloc failure. Try reducing the
|
||||
* aperture so that the gatt size reduces.
|
||||
*/
|
||||
if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
|
||||
goto fail;
|
||||
}
|
||||
sc->gatt = gatt;
|
||||
|
||||
apbase = rman_get_start(sc->agp.as_aperture);
|
||||
aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
|
||||
pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
|
||||
pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
|
||||
pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
|
||||
pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
|
||||
|
||||
error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
|
||||
if (error) {
|
||||
device_printf(dev, "Failed to setup IORRs\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* directory size is 64k */
|
||||
size = AGP_GET_APERTURE(dev) / 1024 / 1024;
|
||||
sc->num_dirs = size / 64;
|
||||
sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
|
||||
sc->pg_offset = 0;
|
||||
if (sc->num_dirs == 0) {
|
||||
sc->num_dirs = 1;
|
||||
sc->num_active_entries /= (64 / size);
|
||||
sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
|
||||
~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
|
||||
}
|
||||
|
||||
/* (G)ATT Base Address */
|
||||
for (i = 0; i < 8; i++) {
|
||||
pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
|
||||
(sc->gatt->ag_physical +
|
||||
(i % sc->num_dirs) * 64 * 1024),
|
||||
4);
|
||||
}
|
||||
|
||||
/* GTLB Control */
|
||||
temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
|
||||
pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
|
||||
|
||||
/* GART Control */
|
||||
temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
|
||||
pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
|
||||
|
||||
return (0);
|
||||
fail:
|
||||
agp_generic_detach(dev);
|
||||
return (ENOMEM);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_nvidia_detach (device_t dev)
|
||||
{
|
||||
struct agp_nvidia_softc *sc = device_get_softc(dev);
|
||||
int error;
|
||||
u_int32_t temp;
|
||||
|
||||
error = agp_generic_detach(dev);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
/* GART Control */
|
||||
temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
|
||||
pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
|
||||
|
||||
/* GTLB Control */
|
||||
temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
|
||||
pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
|
||||
|
||||
/* Put the aperture back the way it started. */
|
||||
AGP_SET_APERTURE(dev, sc->initial_aperture);
|
||||
|
||||
/* restore iorr for previous aperture size */
|
||||
nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
|
||||
sc->initial_aperture);
|
||||
|
||||
agp_free_gatt(sc->gatt);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static u_int32_t
|
||||
agp_nvidia_get_aperture(device_t dev)
|
||||
{
|
||||
u_int8_t key;
|
||||
|
||||
key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
|
||||
return (1 << (24 + (key ? key : 5)));
|
||||
}
|
||||
|
||||
static int
|
||||
agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
|
||||
{
|
||||
u_int8_t val;
|
||||
u_int8_t key;
|
||||
|
||||
switch (aperture) {
|
||||
case (512 * 1024 * 1024): key = 0; break;
|
||||
case (256 * 1024 * 1024): key = 8; break;
|
||||
case (128 * 1024 * 1024): key = 12; break;
|
||||
case (64 * 1024 * 1024): key = 14; break;
|
||||
case (32 * 1024 * 1024): key = 15; break;
|
||||
default:
|
||||
device_printf(dev, "Invalid aperture size (%dMb)\n",
|
||||
aperture / 1024 / 1024);
|
||||
return (EINVAL);
|
||||
}
|
||||
val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
|
||||
pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
|
||||
{
|
||||
struct agp_nvidia_softc *sc = device_get_softc(dev);
|
||||
u_int32_t index;
|
||||
|
||||
if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return (EINVAL);
|
||||
|
||||
index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
|
||||
sc->gatt->ag_virtual[index] = physical;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_nvidia_unbind_page(device_t dev, int offset)
|
||||
{
|
||||
struct agp_nvidia_softc *sc = device_get_softc(dev);
|
||||
u_int32_t index;
|
||||
|
||||
if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return (EINVAL);
|
||||
|
||||
index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
|
||||
sc->gatt->ag_virtual[index] = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_nvidia_flush_tlb (device_t dev, int offset)
|
||||
{
|
||||
struct agp_nvidia_softc *sc;
|
||||
u_int32_t wbc_reg, temp;
|
||||
int i;
|
||||
|
||||
sc = (struct agp_nvidia_softc *)device_get_softc(dev);
|
||||
|
||||
if (sc->wbc_mask) {
|
||||
wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
|
||||
wbc_reg |= sc->wbc_mask;
|
||||
pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
|
||||
|
||||
/* Wait no more than 3 seconds. */
|
||||
for (i = 0; i < 3000; i++) {
|
||||
wbc_reg = pci_read_config(sc->mc1_dev,
|
||||
AGP_NVIDIA_1_WBC, 4);
|
||||
if ((sc->wbc_mask & wbc_reg) == 0)
|
||||
break;
|
||||
else
|
||||
DELAY(1000);
|
||||
}
|
||||
if (i == 3000)
|
||||
device_printf(dev,
|
||||
"TLB flush took more than 3 seconds.\n");
|
||||
}
|
||||
|
||||
/* Flush TLB entries. */
|
||||
for(i = 0; i < 32 + 1; i++)
|
||||
temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
|
||||
for(i = 0; i < 32 + 1; i++)
|
||||
temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#define SYSCFG 0xC0010010
|
||||
#define IORR_BASE0 0xC0010016
|
||||
#define IORR_MASK0 0xC0010017
|
||||
#define AMD_K7_NUM_IORR 2
|
||||
|
||||
static int
|
||||
nvidia_init_iorr(u_int32_t addr, u_int32_t size)
|
||||
{
|
||||
quad_t base, mask, sys;
|
||||
u_int32_t iorr_addr, free_iorr_addr;
|
||||
|
||||
/* Find the iorr that is already used for the addr */
|
||||
/* If not found, determine the uppermost available iorr */
|
||||
free_iorr_addr = AMD_K7_NUM_IORR;
|
||||
for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
|
||||
base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
|
||||
mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
|
||||
|
||||
if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
|
||||
break;
|
||||
|
||||
if ((mask & 0x00000800ULL) == 0)
|
||||
free_iorr_addr = iorr_addr;
|
||||
}
|
||||
|
||||
if (iorr_addr >= AMD_K7_NUM_IORR) {
|
||||
iorr_addr = free_iorr_addr;
|
||||
if (iorr_addr >= AMD_K7_NUM_IORR)
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
base = (addr & ~0xfff) | 0x18;
|
||||
mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
|
||||
wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
|
||||
wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
|
||||
|
||||
sys = rdmsr(SYSCFG);
|
||||
sys |= 0x00100000ULL;
|
||||
wrmsr(SYSCFG, sys);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t agp_nvidia_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, agp_nvidia_probe),
|
||||
DEVMETHOD(device_attach, agp_nvidia_attach),
|
||||
DEVMETHOD(device_detach, agp_nvidia_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
DEVMETHOD(device_suspend, bus_generic_suspend),
|
||||
DEVMETHOD(device_resume, bus_generic_resume),
|
||||
|
||||
/* AGP interface */
|
||||
DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
|
||||
DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
|
||||
DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
|
||||
DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
|
||||
DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
|
||||
|
||||
DEVMETHOD(agp_enable, agp_generic_enable),
|
||||
DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
|
||||
DEVMETHOD(agp_free_memory, agp_generic_free_memory),
|
||||
DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
|
||||
DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t agp_nvidia_driver = {
|
||||
"agp",
|
||||
agp_nvidia_methods,
|
||||
sizeof(struct agp_nvidia_softc),
|
||||
};
|
||||
|
||||
static devclass_t agp_devclass;
|
||||
|
||||
DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
|
||||
MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
|
||||
MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
|
||||
@ -202,4 +202,17 @@
|
||||
#define AGP_I852_GME 0x2
|
||||
#define AGP_I852_GM 0x5
|
||||
|
||||
/*
|
||||
* NVIDIA nForce/nForce2 registers
|
||||
*/
|
||||
#define AGP_NVIDIA_0_APBASE 0x10
|
||||
#define AGP_NVIDIA_0_APSIZE 0x80
|
||||
#define AGP_NVIDIA_1_WBC 0xf0
|
||||
#define AGP_NVIDIA_2_GARTCTRL 0xd0
|
||||
#define AGP_NVIDIA_2_APBASE 0xd8
|
||||
#define AGP_NVIDIA_2_APLIMIT 0xdc
|
||||
#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
|
||||
#define AGP_NVIDIA_3_APBASE 0x50
|
||||
#define AGP_NVIDIA_3_APLIMIT 0x54
|
||||
|
||||
#endif /* !_PCI_AGPREG_H_ */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user