Fix up the sis driver, largely to improve the NatSemi DP83815 support:
- Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
This commit is contained in:
Bill Paul
parent
86bbb70c13
commit
343d203cf1
@ -36,6 +36,9 @@
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* SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
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* available from http://www.sis.com.tw.
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*
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* This driver also supports the NatSemi DP83815. Datasheets are
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* available from http://www.national.com.
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*
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* Written by Bill Paul <wpaul@ee.columbia.edu>
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* Electrical Engineering Department
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* Columbia University, New York City
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@ -447,20 +450,9 @@ static void sis_miibus_statchg(dev)
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device_t dev;
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{
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struct sis_softc *sc;
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struct mii_data *mii;
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sc = device_get_softc(dev);
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mii = device_get_softc(sc->sis_miibus);
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
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SIS_SETBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
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SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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} else {
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SIS_CLRBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
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SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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}
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sis_init(sc);
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return;
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}
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@ -1136,13 +1128,26 @@ static void sis_tick(xsc)
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{
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struct sis_softc *sc;
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struct mii_data *mii;
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struct ifnet *ifp;
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int s;
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s = splimp();
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sc = xsc;
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ifp = &sc->arpcom.ac_if;
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mii = device_get_softc(sc->sis_miibus);
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mii_tick(mii);
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if (!sc->sis_link) {
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mii_pollstat(mii);
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if (mii->mii_media_status & IFM_ACTIVE &&
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IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
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sc->sis_link++;
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if (ifp->if_snd.ifq_head != NULL)
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sis_start(ifp);
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}
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sc->sis_stat_ch = timeout(sis_tick, sc, hz);
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splx(s);
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@ -1176,12 +1181,14 @@ static void sis_intr(arg)
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if ((status & SIS_INTRS) == 0)
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break;
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if ((status & SIS_ISR_TX_OK) ||
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if ((status & SIS_ISR_TX_DESC_OK) ||
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(status & SIS_ISR_TX_ERR) ||
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(status & SIS_ISR_TX_OK) ||
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(status & SIS_ISR_TX_IDLE))
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sis_txeof(sc);
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if (status & SIS_ISR_RX_OK)
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if ((status & SIS_ISR_RX_DESC_OK) ||
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(status & SIS_ISR_RX_OK))
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sis_rxeof(sc);
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if ((status & SIS_ISR_RX_ERR) ||
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@ -1269,6 +1276,9 @@ static void sis_start(ifp)
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sc = ifp->if_softc;
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if (!sc->sis_link)
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return;
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idx = sc->sis_cdata.sis_tx_prod;
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if (ifp->if_flags & IFF_OACTIVE)
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@ -1408,8 +1418,24 @@ static void sis_init(xsc)
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/* Set RX configuration */
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CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG);
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/* Set TX configuration */
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG);
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
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} else {
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CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
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}
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/* Set full/half duplex mode. */
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
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SIS_SETBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
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SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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} else {
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SIS_CLRBIT(sc, SIS_TX_CFG,
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(SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
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SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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}
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/*
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* Enable interrupts.
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@ -1421,7 +1447,24 @@ static void sis_init(xsc)
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SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
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SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
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#ifdef notdef
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mii_mediachg(mii);
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#endif
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/*
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* Page 75 of the DP83815 manual recommends the
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* following register settings "for optimum
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* performance." Note however that at least three
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* of the registers are listed as "reserved" in
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* the register map, so who knows what they do.
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*/
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if (sc->sis_type == SIS_TYPE_83815) {
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
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CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
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CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
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CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
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CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
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}
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE;
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@ -1440,11 +1483,19 @@ static int sis_ifmedia_upd(ifp)
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struct ifnet *ifp;
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{
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struct sis_softc *sc;
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struct mii_data *mii;
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sc = ifp->if_softc;
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if (ifp->if_flags & IFF_UP)
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sis_init(sc);
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mii = device_get_softc(sc->sis_miibus);
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sc->sis_link = 0;
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if (mii->mii_instance) {
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struct mii_softc *miisc;
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for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
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miisc = LIST_NEXT(miisc, mii_list))
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mii_phy_reset(miisc);
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}
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mii_mediachg(mii);
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return(0);
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}
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@ -1560,6 +1611,8 @@ static void sis_stop(sc)
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CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
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CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
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sc->sis_link = 0;
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/*
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* Free data in the RX lists.
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*/
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@ -84,6 +84,14 @@
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#define NS_ANER 0x98
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#define NS_ANNPTR 0x9C
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#define NS_PHY_CR 0xE4
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#define NS_PHY_10BTSCR 0xE8
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#define NS_PHY_PAGE 0xCC
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#define NS_PHY_EXTCFG 0xF0
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#define NS_PHY_DSPCFG 0xF4
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#define NS_PHY_SDCFG 0xF8
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#define NS_PHY_TDATA 0xFC
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#define SIS_CSR_TX_ENABLE 0x00000001
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#define SIS_CSR_TX_DISABLE 0x00000002
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#define SIS_CSR_RX_ENABLE 0x00000004
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@ -205,9 +213,13 @@
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#define SIS_TXDMA_128BYTES 0x00600000
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#define SIS_TXDMA_256BYTES 0x00700000
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#define SIS_TXCFG \
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#define SIS_TXCFG_100 \
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(SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\
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SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1500))
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SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
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#define SIS_TXCFG_10 \
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(SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\
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SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536))
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#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
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#define SIS_RXCFG_DMABURST 0x00700000
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@ -373,6 +385,7 @@ struct sis_softc {
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device_t sis_miibus;
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u_int8_t sis_unit;
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u_int8_t sis_type;
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u_int8_t sis_link;
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struct sis_list_data *sis_ldata;
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struct sis_ring_data sis_cdata;
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struct callout_handle sis_stat_ch;
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