Refactor DTS files for Zynq-based SoCs
- Factor out common part to zynq-7000.dtsi
- Fix problem with Zynq interrupts by using interrupt "triples"
in .dtsi file to differentiate between edge-triggered and
level-triggered interrupts
- cgem driver now recognizes "status" property
Submitted by: Thomas Skibo <thomasskibo@yahoo.com>
Differential Revision: https://reviews.freebsd.org/D6095
This commit is contained in:
Oleksandr Tymoshenko
parent
bac5bedf44
commit
349ef43de4
sys
@ -1,5 +1,5 @@
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/*-
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/*-
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* Copyright (c) 2012 The FreeBSD Foundation
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* Copyright (c) 2016 The FreeBSD Foundation
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -25,24 +25,12 @@
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*
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*
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* $FreeBSD$
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* $FreeBSD$
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*/
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*/
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/dts-v1/;
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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/ {
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model = "zedboard";
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model = "zedboard";
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compatible = "digilent,zedboard";
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compatible = "digilent,zedboard";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&GIC>;
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// cpus {
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// #address-cells = <1>;
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// #size-cells = <0>;
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// cpu@0 {
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// device-type = "cpu";
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// model = "ARM Cortex-A9";
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// };
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// };
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memory {
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memory {
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// First megabyte isn't accessible by all interconnect masters.
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// First megabyte isn't accessible by all interconnect masters.
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@ -50,168 +38,34 @@
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reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
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reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
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};
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};
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// Zynq PS System registers.
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//
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ps7sys@f8000000 {
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device_type = "soc";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xf8000000 0xf10000>;
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// SLCR block
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slcr: slcr@7000 {
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compatible = "xlnx,zy7_slcr";
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reg = <0x0 0x1000>;
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clock-frequency = <33333333>; // 33Mhz PS_CLK
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};
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// Interrupt controller
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GIC: gic {
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compatible = "arm,gic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0xf01000 0x1000>, // distributer registers
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<0xf00100 0x0100>; // CPU if registers
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};
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// L2 cache controller
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pl310@f02000 {
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compatible = "arm,pl310";
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reg = <0xf02000 0x1000>;
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interrupts = <34>;
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interrupt-parent = <&GIC>;
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};
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// Device Config
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devcfg: devcfg@7000 {
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compatible = "xlnx,zy7_devcfg";
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reg = <0x7000 0x1000>;
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interrupts = <40>;
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interrupt-parent = <&GIC>;
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};
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// triple timer counters0,1
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ttc0: ttc@1000 {
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compatible = "xlnx,ttc";
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reg = <0x1000 0x1000>;
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};
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ttc1: ttc@2000 {
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compatible = "xlnx,ttc";
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reg = <0x2000 0x1000>;
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};
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// ARM Cortex A9 TWD Timer
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timer@f00600 {
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compatible = "arm,mpcore-timers";
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clock-frequency = <333333333>; // 333Mhz
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf00200 0x100>, // Global Timer Regs
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<0xf00600 0x20>; // Private Timer Regs
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interrupts = < 27 29 >;
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interrupt-parent = <&GIC>;
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};
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// system watch-dog timer
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swdt@5000 {
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device_type = "watchdog";
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compatible = "xlnx,zy7_wdt";
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reg = <0x5000 0x1000>;
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interrupts = <41>;
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interrupt-parent = <&GIC>;
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};
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scuwdt@f00620 {
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device_type = "watchdog";
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compatible = "arm,mpcore_wdt";
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reg = <0xf00620 0x20>;
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interrupts = <30>;
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interrupt-parent = <&GIC>;
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reset = <1>;
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};
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}; // pssys@f8000000
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// Zynq PS I/O Peripheral registers.
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//
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ps7io@e0000000 {
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device_type = "soc";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0000000 0x300000>;
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// uart0: uart@0000 {
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// device_type = "serial";
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// compatible = "cadence,uart";
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// reg = <0x0000 0x1000>;
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// interrupts = <59>;
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// interrupt-parent = <&GIC>;
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// clock-frequency = <50000000>;
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// };
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uart1: uart@1000 {
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device_type = "serial";
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compatible = "cadence,uart";
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reg = <0x1000 0x1000>;
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interrupts = <82>;
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interrupt-parent = <&GIC>;
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clock-frequency = <50000000>;
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current-speed = <115200>;
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};
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gpio: gpio@a000 {
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compatible = "xlnx,zy7_gpio";
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reg = <0xa000 0x1000>;
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interrupts = <52>;
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interrupt-parent = <&GIC>;
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};
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// GigE
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eth0: eth@b000 {
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// device_type = "network";
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compatible = "cadence,gem";
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reg = <0xb000 0x1000>;
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interrupts = <54 55>;
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interrupt-parent = <&GIC>;
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ref-clock-num = <0>;
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};
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// SDIO
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sdhci0: sdhci@100000 {
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compatible = "xlnx,zy7_sdhci";
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reg = <0x100000 0x1000>;
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interrupts = <56>;
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interrupt-parent = <&GIC>;
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max-frequency = <50000000>;
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};
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// QSPI
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qspi0: qspi@d000 {
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compatible = "xlnx,zy7_qspi";
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reg = <0xd000 0x1000>;
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interrupts = <51>;
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interrupt-parent = <&GIC>;
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spi-clock = <50000000>;
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ref-clock = <190476000>;
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};
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// USB
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ehci0: ehci@2000 {
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compatible = "xlnx,zy7_ehci";
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reg = <0x2000 0x1000>;
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interrupts = <53>;
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interrupt-parent = <&GIC>;
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phy_vbus_ext;
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};
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}; // ps7io@e0000000
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chosen {
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chosen {
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stdin = &uart1;
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stdin = &uart1;
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stdout = &uart1;
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stdout = &uart1;
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};
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};
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};
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};
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&slcr {
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clock-frequency = <33333333>; // 33Mhz PS_CLK
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};
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&global_timer {
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clock-frequency = <333333333>; // 333Mhz
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};
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&uart1 {
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status = "okay";
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};
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ð0 {
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status = "okay";
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};
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&sdhci0 {
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status = "okay";
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};
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&ehci0 {
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status = "okay";
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phy_vbus_ext;
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};
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@ -1,216 +1,69 @@
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/*-
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/*-
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* Copyright (c) 2015 The FreeBSD Foundation
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* Copyright (c) 2016 The FreeBSD Foundation
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* modification, are permitted provided that the following conditions
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* are met:
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* documentation and/or other materials provided with the distribution.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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* SUCH DAMAGE.
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*
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*
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* $FreeBSD$
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* $FreeBSD$
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*/
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*/
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/dts-v1/;
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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/ {
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model = "zybo";
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model = "zybo";
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compatible = "digilent,zybo";
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compatible = "digilent,zybo";
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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interrupt-parent = <&GIC>;
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// First megabyte isn't accessible by all interconnect masters.
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device_type = "memory";
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// cpus {
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reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
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// #address-cells = <1>;
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};
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// #size-cells = <0>;
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// cpu@0 {
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chosen {
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// device-type = "cpu";
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stdin = &uart1;
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// model = "ARM Cortex-A9";
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stdout = &uart1;
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// };
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};
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// };
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};
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memory {
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&slcr {
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// First megabyte isn't accessible by all interconnect masters.
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clock-frequency = <50000000>; // 50Mhz PS_CLK
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device_type = "memory";
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};
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reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
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};
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&global_timer {
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clock-frequency = <325000000>; // 325Mhz
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// Zynq PS System registers.
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};
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//
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ps7sys@f8000000 {
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&uart1 {
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device_type = "soc";
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status = "okay";
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compatible = "simple-bus";
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};
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#address-cells = <1>;
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#size-cells = <1>;
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ð0 {
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ranges = <0x0 0xf8000000 0xf10000>;
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status = "okay";
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};
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// SLCR block
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slcr: slcr@7000 {
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&sdhci0 {
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compatible = "xlnx,zy7_slcr";
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status = "okay";
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reg = <0x0 0x1000>;
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};
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clock-frequency = <50000000>; // 50Mhz PS_CLK
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};
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&ehci0 {
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status = "okay";
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// Interrupt controller
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};
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GIC: gic {
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compatible = "arm,gic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0xf01000 0x1000>, // distributer registers
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<0xf00100 0x0100>; // CPU if registers
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};
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// L2 cache controller
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pl310@f02000 {
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compatible = "arm,pl310";
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reg = <0xf02000 0x1000>;
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interrupts = <34>;
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interrupt-parent = <&GIC>;
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};
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// Device Config
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devcfg: devcfg@7000 {
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compatible = "xlnx,zy7_devcfg";
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reg = <0x7000 0x1000>;
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interrupts = <40>;
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interrupt-parent = <&GIC>;
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};
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// triple timer counters0,1
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ttc0: ttc@1000 {
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compatible = "xlnx,ttc";
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reg = <0x1000 0x1000>;
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};
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ttc1: ttc@2000 {
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compatible = "xlnx,ttc";
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reg = <0x2000 0x1000>;
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};
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// ARM Cortex A9 TWD Timer
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timer@f00600 {
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compatible = "arm,mpcore-timers";
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clock-frequency = <325000000>; // 325Mhz
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf00200 0x100>, // Global Timer Regs
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<0xf00600 0x20>; // Private Timer Regs
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interrupts = < 27 29 >;
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interrupt-parent = <&GIC>;
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};
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// system watch-dog timer
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swdt@5000 {
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device_type = "watchdog";
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compatible = "xlnx,zy7_wdt";
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reg = <0x5000 0x1000>;
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interrupts = <41>;
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interrupt-parent = <&GIC>;
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};
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scuwdt@f00620 {
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device_type = "watchdog";
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compatible = "arm,mpcore_wdt";
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reg = <0xf00620 0x20>;
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interrupts = <30>;
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interrupt-parent = <&GIC>;
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reset = <1>;
|
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};
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}; // pssys@f8000000
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|
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// Zynq PS I/O Peripheral registers.
|
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//
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ps7io@e0000000 {
|
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device_type = "soc";
|
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compatible = "simple-bus";
|
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#address-cells = <1>;
|
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#size-cells = <1>;
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ranges = <0x0 0xe0000000 0x300000>;
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// uart0: uart@0000 {
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// device_type = "serial";
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||||||
// compatible = "cadence,uart";
|
|
||||||
// reg = <0x0000 0x1000>;
|
|
||||||
// interrupts = <59>;
|
|
||||||
// interrupt-parent = <&GIC>;
|
|
||||||
// clock-frequency = <50000000>;
|
|
||||||
// };
|
|
||||||
|
|
||||||
uart1: uart@1000 {
|
|
||||||
device_type = "serial";
|
|
||||||
compatible = "cadence,uart";
|
|
||||||
reg = <0x1000 0x1000>;
|
|
||||||
interrupts = <82>;
|
|
||||||
interrupt-parent = <&GIC>;
|
|
||||||
clock-frequency = <50000000>;
|
|
||||||
current-speed = <115200>;
|
|
||||||
};
|
|
||||||
|
|
||||||
gpio: gpio@a000 {
|
|
||||||
compatible = "xlnx,zy7_gpio";
|
|
||||||
reg = <0xa000 0x1000>;
|
|
||||||
interrupts = <52>;
|
|
||||||
interrupt-parent = <&GIC>;
|
|
||||||
};
|
|
||||||
|
|
||||||
// GigE
|
|
||||||
eth0: eth@b000 {
|
|
||||||
// device_type = "network";
|
|
||||||
|
|
||||||
compatible = "cadence,gem";
|
|
||||||
reg = <0xb000 0x1000>;
|
|
||||||
interrupts = <54 55>;
|
|
||||||
interrupt-parent = <&GIC>;
|
|
||||||
ref-clock-num = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
// SDIO
|
|
||||||
sdhci0: sdhci@100000 {
|
|
||||||
compatible = "xlnx,zy7_sdhci";
|
|
||||||
reg = <0x100000 0x1000>;
|
|
||||||
interrupts = <56>;
|
|
||||||
interrupt-parent = <&GIC>;
|
|
||||||
max-frequency = <50000000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
// QSPI
|
|
||||||
qspi0: qspi@d000 {
|
|
||||||
compatible = "xlnx,zy7_qspi";
|
|
||||||
reg = <0xd000 0x1000>;
|
|
||||||
interrupts = <51>;
|
|
||||||
interrupt-parent = <&GIC>;
|
|
||||||
spi-clock = <50000000>;
|
|
||||||
ref-clock = <200000000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
// USB
|
|
||||||
ehci0: ehci@2000 {
|
|
||||||
compatible = "xlnx,zy7_ehci";
|
|
||||||
reg = <0x2000 0x1000>;
|
|
||||||
interrupts = <53>;
|
|
||||||
interrupt-parent = <&GIC>;
|
|
||||||
};
|
|
||||||
|
|
||||||
}; // ps7io@e0000000
|
|
||||||
|
|
||||||
chosen {
|
|
||||||
stdin = &uart1;
|
|
||||||
stdout = &uart1;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|||||||
225
sys/boot/fdt/dts/arm/zynq-7000.dtsi
Normal file
225
sys/boot/fdt/dts/arm/zynq-7000.dtsi
Normal file
@ -0,0 +1,225 @@
|
|||||||
|
/*-
|
||||||
|
* Copyright (c) 2016 The FreeBSD Foundation
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* $FreeBSD$
|
||||||
|
*/
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "xlnx,zynq-7000";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
|
||||||
|
// Zynq PS System registers.
|
||||||
|
//
|
||||||
|
ps7sys@f8000000 {
|
||||||
|
device_type = "soc";
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x0 0xf8000000 0xf10000>;
|
||||||
|
|
||||||
|
// SLCR block
|
||||||
|
slcr: slcr@7000 {
|
||||||
|
compatible = "xlnx,zy7_slcr";
|
||||||
|
reg = <0x0 0x1000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Interrupt controller
|
||||||
|
GIC: gic {
|
||||||
|
compatible = "arm,gic";
|
||||||
|
interrupt-controller;
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
reg = <0xf01000 0x1000>, // distributer registers
|
||||||
|
<0xf00100 0x0100>; // CPU if registers
|
||||||
|
};
|
||||||
|
|
||||||
|
// L2 cache controller
|
||||||
|
pl310@f02000 {
|
||||||
|
compatible = "arm,pl310";
|
||||||
|
reg = <0xf02000 0x1000>;
|
||||||
|
interrupts = <0 2 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Device Config
|
||||||
|
devcfg: devcfg@7000 {
|
||||||
|
compatible = "xlnx,zy7_devcfg";
|
||||||
|
reg = <0x7000 0x1000>;
|
||||||
|
interrupts = <0 8 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// triple timer counters0,1
|
||||||
|
ttc0: ttc@1000 {
|
||||||
|
compatible = "xlnx,ttc";
|
||||||
|
reg = <0x1000 0x1000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ttc1: ttc@2000 {
|
||||||
|
compatible = "xlnx,ttc";
|
||||||
|
reg = <0x2000 0x1000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// ARM Cortex A9 TWD Timer
|
||||||
|
global_timer: timer@f00600 {
|
||||||
|
compatible = "arm,mpcore-timers";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0xf00200 0x100>, // Global Timer Regs
|
||||||
|
<0xf00600 0x20>; // Private Timer Regs
|
||||||
|
interrupts = <1 11 1>, <1 13 1>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// system watch-dog timer
|
||||||
|
swdt@5000 {
|
||||||
|
device_type = "watchdog";
|
||||||
|
compatible = "xlnx,zy7_wdt";
|
||||||
|
reg = <0x5000 0x1000>;
|
||||||
|
interrupts = <0 9 1>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
scuwdt@f00620 {
|
||||||
|
device_type = "watchdog";
|
||||||
|
compatible = "arm,mpcore_wdt";
|
||||||
|
reg = <0xf00620 0x20>;
|
||||||
|
interrupts = <1 14 1>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
reset = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
}; // pssys@f8000000
|
||||||
|
|
||||||
|
// Zynq PS I/O Peripheral registers.
|
||||||
|
//
|
||||||
|
ps7io@e0000000 {
|
||||||
|
device_type = "soc";
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x0 0xe0000000 0x300000>;
|
||||||
|
|
||||||
|
// UART controllers
|
||||||
|
uart0: uart@0000 {
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "cadence,uart";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0x0000 0x1000>;
|
||||||
|
interrupts = <0 27 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
clock-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1: uart@1000 {
|
||||||
|
device_type = "serial";
|
||||||
|
compatible = "cadence,uart";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0x1000 0x1000>;
|
||||||
|
interrupts = <0 50 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
clock-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// USB controllers
|
||||||
|
ehci0: ehci@2000 {
|
||||||
|
compatible = "xlnx,zy7_ehci";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0x2000 0x1000>;
|
||||||
|
interrupts = <0 21 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ehci1: ehci@3000 {
|
||||||
|
compatible = "xlnx,zy7_ehci";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0x3000 0x1000>;
|
||||||
|
interrupts = <0 44 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// GPIO controller
|
||||||
|
gpio: gpio@a000 {
|
||||||
|
compatible = "xlnx,zy7_gpio";
|
||||||
|
reg = <0xa000 0x1000>;
|
||||||
|
interrupts = <0 20 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Gigabit Ethernet controllers
|
||||||
|
eth0: eth@b000 {
|
||||||
|
device_type = "network";
|
||||||
|
compatible = "cadence,gem";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0xb000 0x1000>;
|
||||||
|
interrupts = <0 22 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
ref-clock-num = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
eth1: eth@c000 {
|
||||||
|
device_type = "network";
|
||||||
|
compatible = "cadence,gem";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0xc000 0x1000>;
|
||||||
|
interrupts = <0 45 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
ref-clock-num = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Quad-SPI controller
|
||||||
|
qspi0: qspi@d000 {
|
||||||
|
compatible = "xlnx,zy7_qspi";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0xd000 0x1000>;
|
||||||
|
interrupts = <0 19 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
spi-clock = <50000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// SDIO controllers
|
||||||
|
sdhci0: sdhci@100000 {
|
||||||
|
compatible = "xlnx,zy7_sdhci";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0x100000 0x1000>;
|
||||||
|
interrupts = <0 24 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
max-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sdhci1: sdhci@101000 {
|
||||||
|
compatible = "xlnx,zy7_sdhci";
|
||||||
|
status = "disabled";
|
||||||
|
reg = <0x101000 0x1000>;
|
||||||
|
interrupts = <0 47 4>;
|
||||||
|
interrupt-parent = <&GIC>;
|
||||||
|
max-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
}; // ps7io@e0000000
|
||||||
|
};
|
||||||
|
|
||||||
@ -1630,6 +1630,9 @@ static int
|
|||||||
cgem_probe(device_t dev)
|
cgem_probe(device_t dev)
|
||||||
{
|
{
|
||||||
|
|
||||||
|
if (!ofw_bus_status_okay(dev))
|
||||||
|
return (ENXIO);
|
||||||
|
|
||||||
if (!ofw_bus_is_compatible(dev, "cadence,gem"))
|
if (!ofw_bus_is_compatible(dev, "cadence,gem"))
|
||||||
return (ENXIO);
|
return (ENXIO);
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user