Complete and merge the list between Sandy/Ivy bridge of events
that can run on specific PMC. MFC after: 1 month
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@ -1695,35 +1695,28 @@ iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
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}
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static int
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iap_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri)
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iap_event_sb_ib_ok_on_counter(enum pmc_event pe, int ri)
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{
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uint32_t mask;
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switch (pe) {
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/*
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* Events valid only on counter 2.
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*/
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/* Events valid only on counter 0. */
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case PMC_EV_IAP_EVENT_B7H_01H:
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mask = 0x1;
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break;
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/* Events valid only on counter 1. */
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case PMC_EV_IAP_EVENT_C0H_01H:
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mask = 0x1;
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break;
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/* Events valid only on counter 2. */
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case PMC_EV_IAP_EVENT_48H_01H:
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mask = 0x4;
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break;
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default:
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mask = ~0; /* Any row index is ok. */
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}
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return (mask & (1 << ri));
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}
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static int
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iap_event_ivybridge_ok_on_counter(enum pmc_event pe, int ri)
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{
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uint32_t mask;
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switch (pe) {
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/*
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* Events valid only on counter 2.
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*/
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case PMC_EV_IAP_EVENT_48H_01H:
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mask = 0x4;
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/* Events valid only on counter 3. */
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case PMC_EV_IAP_EVENT_BBH_01H:
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case PMC_EV_IAP_EVENT_CDH_01H:
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case PMC_EV_IAP_EVENT_CDH_02H:
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mask = 0x8;
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break;
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default:
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mask = ~0; /* Any row index is ok. */
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@ -1808,12 +1801,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
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if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
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return (EINVAL);
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break;
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case PMC_CPU_INTEL_IVYBRIDGE:
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if (iap_event_ivybridge_ok_on_counter(ev, ri) == 0)
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return (EINVAL);
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break;
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case PMC_CPU_INTEL_SANDYBRIDGE:
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if (iap_event_sandybridge_ok_on_counter(ev, ri) == 0)
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case PMC_CPU_INTEL_IVYBRIDGE:
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if (iap_event_sb_ib_ok_on_counter(ev, ri) == 0)
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return (EINVAL);
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break;
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case PMC_CPU_INTEL_WESTMERE:
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