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[ath_hal] modify the xmit code to use temporary variables for setting qmisc/dmisc.

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This is in preparation for some other TDMA fixes which will hopefully
end with having working TDMA.

But, it does avoid lots of read/modify/writes in the txq setup path.
This commit is contained in:
Adrian Chadd 2016-06-08 16:26:44 +00:00
parent dd77085237
commit 3648197a1b
1 changed files with 23 additions and 38 deletions
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61
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_xmit.c
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@ -288,6 +288,7 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_TX_QUEUE_INFO *qi;
u_int32_t cw_min, chan_cw_min, value;
uint32_t qmisc, dmisc;
if (q >= p_cap->halTotalQueues) {
HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
@ -335,17 +336,15 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
/* enable early termination on the QCU */
OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ;
/* enable DCU to wait for next fragment from QCU */
if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) {
/* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff
* threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */
OS_REG_WRITE(ah, AR_DMISC(q),
AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1;
} else {
OS_REG_WRITE(ah, AR_DMISC(q),
AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2;
}
/* multiqueue support */
@ -355,11 +354,9 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
SM(qi->tqi_cbrOverflowLimit,
AR_Q_CBRCFG_OVF_THRESH));
OS_REG_WRITE(ah, AR_QMISC(q),
OS_REG_READ(ah, AR_QMISC(q)) |
AR_Q_MISC_FSP_CBR |
qmisc |= AR_Q_MISC_FSP_CBR |
(qi->tqi_cbrOverflowLimit ?
AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0);
}
if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
@ -374,34 +371,27 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
if (qi->tqi_burstTime &&
(qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
{
OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) |
AR_Q_MISC_RDYTIME_EXP_POLICY);
qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY;
}
if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
AR_D_MISC_POST_FR_BKOFF_DIS);
dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
}
if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
AR_D_MISC_FRAG_BKOFF_EN);
dmisc |= AR_D_MISC_FRAG_BKOFF_EN;
}
switch (qi->tqi_type) {
case HAL_TX_QUEUE_BEACON: /* beacon frames */
OS_REG_WRITE(ah, AR_QMISC(q),
OS_REG_READ(ah, AR_QMISC(q))
| AR_Q_MISC_FSP_DBA_GATED
qmisc |= AR_Q_MISC_FSP_DBA_GATED
| AR_Q_MISC_BEACON_USE
| AR_Q_MISC_CBR_INCR_DIS1);
| AR_Q_MISC_CBR_INCR_DIS1;
OS_REG_WRITE(ah, AR_DMISC(q),
OS_REG_READ(ah, AR_DMISC(q))
| (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
dmisc |= (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
| AR_D_MISC_BEACON_USE
| AR_D_MISC_POST_FR_BKOFF_DIS);
| AR_D_MISC_POST_FR_BKOFF_DIS;
/* XXX cwmin and cwmax should be 0 for beacon queue */
if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) {
OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
@ -416,11 +406,9 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
* not properly refreshing the Tx descriptor if
* the TXE clear setting is used.
*/
OS_REG_WRITE(ah, AR_QMISC(q),
OS_REG_READ(ah, AR_QMISC(q))
| AR_Q_MISC_FSP_DBA_GATED
qmisc |= AR_Q_MISC_FSP_DBA_GATED
| AR_Q_MISC_CBR_INCR_DIS1
| AR_Q_MISC_CBR_INCR_DIS0);
| AR_Q_MISC_CBR_INCR_DIS0;
if (qi->tqi_readyTime) {
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
@ -446,9 +434,8 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
AR_Q_RDYTIMECFG_EN);
}
OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
| (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
dmisc |= (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
AR_D_MISC_ARB_LOCKOUT_CNTRL_S);
break;
case HAL_TX_QUEUE_PSPOLL:
/*
@ -459,12 +446,10 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
* non-TIM elements and send PS-poll PS poll processing
* will be done in software
*/
OS_REG_WRITE(ah, AR_QMISC(q),
OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
qmisc |= AR_Q_MISC_CBR_INCR_DIS1;
break;
case HAL_TX_QUEUE_UAPSD:
OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
| AR_D_MISC_POST_FR_BKOFF_DIS);
dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
break;
default: /* NB: silence compiler */
break;
@ -479,15 +464,15 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
* queue_info->dcumode.
*/
if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
OS_REG_WRITE(ah, AR_DMISC(q),
OS_REG_READ(ah, AR_DMISC(q)) |
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
AR_D_MISC_ARB_LOCKOUT_CNTRL) |
AR_D_MISC_POST_FR_BKOFF_DIS);
AR_D_MISC_POST_FR_BKOFF_DIS;
}
#endif
OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
OS_REG_WRITE(ah, AR_QMISC(q), qmisc);
OS_REG_WRITE(ah, AR_DMISC(q), dmisc);
/*
* Always update the secondary interrupt mask registers - this