Switch to C99 exact-width types.
This commit is contained in:
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3f13ffab71
commit
3753228779
@ -192,13 +192,13 @@ ia64_mf_a(void)
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* Flush Cache.
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* Flush Cache.
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*/
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*/
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static __inline void
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static __inline void
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ia64_fc(u_int64_t va)
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ia64_fc(uint64_t va)
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{
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{
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__asm __volatile("fc %0" :: "r"(va));
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__asm __volatile("fc %0" :: "r"(va));
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}
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}
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static __inline void
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static __inline void
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ia64_fc_i(u_int64_t va)
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ia64_fc_i(uint64_t va)
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{
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{
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__asm __volatile("fc.i %0" :: "r"(va));
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__asm __volatile("fc.i %0" :: "r"(va));
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}
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}
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@ -215,10 +215,10 @@ ia64_sync_i(void)
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/*
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/*
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* Calculate address in VHPT for va.
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* Calculate address in VHPT for va.
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*/
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*/
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static __inline u_int64_t
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static __inline uint64_t
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ia64_thash(u_int64_t va)
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ia64_thash(uint64_t va)
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{
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{
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u_int64_t result;
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uint64_t result;
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__asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
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__asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
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return result;
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return result;
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}
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}
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@ -226,10 +226,10 @@ ia64_thash(u_int64_t va)
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/*
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/*
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* Calculate VHPT tag for va.
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* Calculate VHPT tag for va.
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*/
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*/
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static __inline u_int64_t
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static __inline uint64_t
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ia64_ttag(u_int64_t va)
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ia64_ttag(uint64_t va)
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{
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{
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u_int64_t result;
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uint64_t result;
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__asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
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__asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
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return result;
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return result;
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}
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}
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@ -237,10 +237,10 @@ ia64_ttag(u_int64_t va)
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/*
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/*
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* Convert virtual address to physical.
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* Convert virtual address to physical.
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*/
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*/
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static __inline u_int64_t
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static __inline uint64_t
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ia64_tpa(u_int64_t va)
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ia64_tpa(uint64_t va)
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{
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{
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u_int64_t result;
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uint64_t result;
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__asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
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__asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
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return result;
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return result;
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}
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}
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@ -249,7 +249,7 @@ ia64_tpa(u_int64_t va)
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* Generate a ptc.e instruction.
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* Generate a ptc.e instruction.
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*/
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*/
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static __inline void
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static __inline void
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ia64_ptc_e(u_int64_t v)
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ia64_ptc_e(uint64_t v)
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{
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{
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__asm __volatile("ptc.e %0;; srlz.i;;" :: "r"(v));
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__asm __volatile("ptc.e %0;; srlz.i;;" :: "r"(v));
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}
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}
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@ -258,7 +258,7 @@ ia64_ptc_e(u_int64_t v)
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* Generate a ptc.g instruction.
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* Generate a ptc.g instruction.
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*/
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*/
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static __inline void
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static __inline void
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ia64_ptc_g(u_int64_t va, u_int64_t log2size)
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ia64_ptc_g(uint64_t va, uint64_t log2size)
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{
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{
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__asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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__asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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}
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}
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@ -267,7 +267,7 @@ ia64_ptc_g(u_int64_t va, u_int64_t log2size)
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* Generate a ptc.ga instruction.
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* Generate a ptc.ga instruction.
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*/
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*/
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static __inline void
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static __inline void
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ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
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ia64_ptc_ga(uint64_t va, uint64_t log2size)
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{
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{
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__asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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__asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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}
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}
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@ -276,7 +276,7 @@ ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
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* Generate a ptc.l instruction.
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* Generate a ptc.l instruction.
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*/
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*/
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static __inline void
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static __inline void
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ia64_ptc_l(u_int64_t va, u_int64_t log2size)
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ia64_ptc_l(uint64_t va, uint64_t log2size)
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{
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{
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__asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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__asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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}
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}
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@ -352,10 +352,10 @@ ia64_st8(uint64_t *p, uint64_t v)
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/*
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/*
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* Read the value of psr.
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* Read the value of psr.
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*/
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*/
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static __inline u_int64_t
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static __inline uint64_t
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ia64_get_psr(void)
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ia64_get_psr(void)
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{
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{
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u_int64_t result;
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uint64_t result;
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__asm __volatile("mov %0=psr;;" : "=r" (result));
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__asm __volatile("mov %0=psr;;" : "=r" (result));
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return result;
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return result;
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}
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}
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@ -366,16 +366,16 @@ ia64_get_psr(void)
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#define IA64_AR(name) \
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#define IA64_AR(name) \
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\
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\
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static __inline u_int64_t \
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static __inline uint64_t \
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ia64_get_##name(void) \
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ia64_get_##name(void) \
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{ \
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{ \
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u_int64_t result; \
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uint64_t result; \
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__asm __volatile("mov %0=ar." #name : "=r" (result)); \
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__asm __volatile("mov %0=ar." #name : "=r" (result)); \
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return result; \
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return result; \
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} \
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} \
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\
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\
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static __inline void \
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static __inline void \
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ia64_set_##name(u_int64_t v) \
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ia64_set_##name(uint64_t v) \
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{ \
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{ \
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__asm __volatile("mov ar." #name "=%0;;" :: "r" (v)); \
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__asm __volatile("mov ar." #name "=%0;;" :: "r" (v)); \
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}
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}
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@ -422,16 +422,16 @@ IA64_AR(ec)
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#define IA64_CR(name) \
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#define IA64_CR(name) \
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\
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\
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static __inline u_int64_t \
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static __inline uint64_t \
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ia64_get_##name(void) \
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ia64_get_##name(void) \
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{ \
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{ \
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u_int64_t result; \
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uint64_t result; \
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__asm __volatile("mov %0=cr." #name : "=r" (result)); \
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__asm __volatile("mov %0=cr." #name : "=r" (result)); \
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return result; \
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return result; \
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} \
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} \
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\
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\
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static __inline void \
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static __inline void \
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ia64_set_##name(u_int64_t v) \
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ia64_set_##name(uint64_t v) \
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{ \
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{ \
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__asm __volatile("mov cr." #name "=%0;;" :: "r" (v)); \
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__asm __volatile("mov cr." #name "=%0;;" :: "r" (v)); \
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}
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}
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@ -472,7 +472,7 @@ IA64_CR(lrr1)
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* Write a region register.
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* Write a region register.
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*/
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*/
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static __inline void
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static __inline void
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ia64_set_rr(u_int64_t rrbase, u_int64_t v)
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ia64_set_rr(uint64_t rrbase, uint64_t v)
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{
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{
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__asm __volatile("mov rr[%0]=%1"
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__asm __volatile("mov rr[%0]=%1"
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:: "r"(rrbase), "r"(v) : "memory");
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:: "r"(rrbase), "r"(v) : "memory");
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@ -481,10 +481,10 @@ ia64_set_rr(u_int64_t rrbase, u_int64_t v)
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/*
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/*
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* Read a CPUID register.
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* Read a CPUID register.
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*/
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*/
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static __inline u_int64_t
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static __inline uint64_t
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ia64_get_cpuid(int i)
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ia64_get_cpuid(int i)
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{
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{
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u_int64_t result;
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uint64_t result;
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__asm __volatile("mov %0=cpuid[%1]"
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__asm __volatile("mov %0=cpuid[%1]"
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: "=r" (result) : "r"(i));
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: "=r" (result) : "r"(i));
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return result;
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return result;
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@ -75,7 +75,7 @@ struct md_page {
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struct pmap {
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struct pmap {
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struct mtx pm_mtx;
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struct mtx pm_mtx;
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TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
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TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
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u_int32_t pm_rid[5]; /* base RID for pmap */
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uint32_t pm_rid[5]; /* base RID for pmap */
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struct pmap_statistics pm_stats; /* pmap statistics */
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struct pmap_statistics pm_stats; /* pmap statistics */
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uint32_t pm_gen_count; /* generation count (pmap lock dropped) */
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uint32_t pm_gen_count; /* generation count (pmap lock dropped) */
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u_int pm_retries;
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u_int pm_retries;
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@ -41,12 +41,12 @@
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/*
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/*
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* Type of run queue status word.
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* Type of run queue status word.
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*/
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*/
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typedef u_int64_t rqb_word_t;
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typedef uint64_t rqb_word_t;
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static __inline u_int64_t
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static __inline uint64_t
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__popcnt(u_int64_t bits)
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__popcnt(uint64_t bits)
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{
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{
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u_int64_t result;
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uint64_t result;
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__asm __volatile("popcnt %0=%1" : "=r" (result) : "r" (bits));
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__asm __volatile("popcnt %0=%1" : "=r" (result) : "r" (bits));
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return result;
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return result;
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@ -32,68 +32,68 @@
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struct sal_system_table {
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struct sal_system_table {
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char sal_signature[4];
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char sal_signature[4];
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#define SAL_SIGNATURE "SST_"
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#define SAL_SIGNATURE "SST_"
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u_int32_t sal_length;
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uint32_t sal_length;
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u_int8_t sal_rev[2];
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uint8_t sal_rev[2];
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u_int16_t sal_entry_count;
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uint16_t sal_entry_count;
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u_int8_t sal_checksum;
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uint8_t sal_checksum;
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u_int8_t sal_reserved1[7];
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uint8_t sal_reserved1[7];
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u_int8_t sal_a_version[2];
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uint8_t sal_a_version[2];
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u_int8_t sal_b_version[2];
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uint8_t sal_b_version[2];
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char sal_oem_id[32];
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char sal_oem_id[32];
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char sal_product_id[32];
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char sal_product_id[32];
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u_int8_t sal_reserved2[8];
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uint8_t sal_reserved2[8];
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};
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};
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struct sal_entrypoint_descriptor {
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struct sal_entrypoint_descriptor {
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u_int8_t sale_type; /* == 0 */
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uint8_t sale_type; /* == 0 */
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u_int8_t sale_reserved1[7];
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uint8_t sale_reserved1[7];
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u_int64_t sale_pal_proc;
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uint64_t sale_pal_proc;
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u_int64_t sale_sal_proc;
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uint64_t sale_sal_proc;
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u_int64_t sale_sal_gp;
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uint64_t sale_sal_gp;
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u_int8_t sale_reserved2[16];
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uint8_t sale_reserved2[16];
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};
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};
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struct sal_memory_descriptor {
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struct sal_memory_descriptor {
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u_int8_t sale_type; /* == 1 */
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uint8_t sale_type; /* == 1 */
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u_int8_t sale_need_virtual;
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uint8_t sale_need_virtual;
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u_int8_t sale_current_attribute;
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uint8_t sale_current_attribute;
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u_int8_t sale_access_rights;
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uint8_t sale_access_rights;
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u_int8_t sale_supported_attributes;
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uint8_t sale_supported_attributes;
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u_int8_t sale_reserved1;
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uint8_t sale_reserved1;
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u_int8_t sale_memory_type[2];
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uint8_t sale_memory_type[2];
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u_int64_t sale_physical_address;
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uint64_t sale_physical_address;
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u_int32_t sale_length;
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uint32_t sale_length;
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u_int8_t sale_reserved2[12];
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uint8_t sale_reserved2[12];
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};
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};
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struct sal_platform_descriptor {
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struct sal_platform_descriptor {
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u_int8_t sale_type; /* == 2 */
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uint8_t sale_type; /* == 2 */
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u_int8_t sale_features;
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uint8_t sale_features;
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u_int8_t sale_reserved[14];
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uint8_t sale_reserved[14];
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};
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};
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struct sal_tr_descriptor {
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struct sal_tr_descriptor {
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u_int8_t sale_type; /* == 3 */
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uint8_t sale_type; /* == 3 */
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u_int8_t sale_register_type;
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uint8_t sale_register_type;
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u_int8_t sale_register_number;
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uint8_t sale_register_number;
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u_int8_t sale_reserved1[5];
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uint8_t sale_reserved1[5];
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u_int64_t sale_virtual_address;
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uint64_t sale_virtual_address;
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u_int64_t sale_page_size;
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uint64_t sale_page_size;
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u_int8_t sale_reserved2[8];
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uint8_t sale_reserved2[8];
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};
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};
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struct sal_ptc_cache_descriptor {
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struct sal_ptc_cache_descriptor {
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u_int8_t sale_type; /* == 4 */
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uint8_t sale_type; /* == 4 */
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u_int8_t sale_reserved[3];
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uint8_t sale_reserved[3];
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u_int32_t sale_domains;
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uint32_t sale_domains;
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u_int64_t sale_address;
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uint64_t sale_address;
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};
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};
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struct sal_ap_wakeup_descriptor {
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struct sal_ap_wakeup_descriptor {
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u_int8_t sale_type; /* == 5 */
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uint8_t sale_type; /* == 5 */
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u_int8_t sale_mechanism;
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uint8_t sale_mechanism;
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u_int8_t sale_reserved[6];
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uint8_t sale_reserved[6];
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u_int64_t sale_vector;
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uint64_t sale_vector;
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};
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};
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/*
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/*
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@ -128,12 +128,11 @@ struct sal_ap_wakeup_descriptor {
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struct ia64_sal_result {
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struct ia64_sal_result {
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int64_t sal_status;
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int64_t sal_status;
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u_int64_t sal_result[3];
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uint64_t sal_result[3];
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};
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};
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typedef struct ia64_sal_result sal_entry_t
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typedef struct ia64_sal_result sal_entry_t(uint64_t, uint64_t, uint64_t,
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(u_int64_t, u_int64_t, u_int64_t, u_int64_t,
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uint64_t, uint64_t, uint64_t, uint64_t, uint64_t);
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u_int64_t, u_int64_t, u_int64_t, u_int64_t);
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extern sal_entry_t *ia64_sal_entry;
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extern sal_entry_t *ia64_sal_entry;
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@ -129,7 +129,7 @@
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/*
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/*
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* Manipulating region bits of an address.
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* Manipulating region bits of an address.
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*/
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*/
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#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61)
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#define IA64_RR_BASE(n) (((uint64_t) (n)) << 61)
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#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1))
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#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1))
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#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
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#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
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