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Update our Allwinner DTS to latest DTS changes in Linux 4.10

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This commit is contained in:
Emmanuel Vadot 2017-03-07 13:59:30 +00:00
parent d7d085358c
commit 39e6bebd91
2 changed files with 31 additions and 101 deletions
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120
sys/boot/fdt/dts/arm/h3.dtsi
View File

@ -26,91 +26,29 @@
* $FreeBSD$
*/
#include <dt-bindings/clock/sun4i-a10-pll2.h>
/ {
cpus {
cpu0: cpu@0 {
clocks = <&cpu>;
clocks = <&ccu CLK_CPUX>;
clock-latency = <2000000>;
};
};
clocks {
pll2: clk@01c20008 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-h3-pll2-clk";
reg = <0x01c20008 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll2-1x", "pll2-2x",
"pll2-4x", "pll2-8x";
};
ths_clk: clk@1c20074 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-h3-ths-clk";
reg = <0x01c20074 0x4>;
clocks = <&osc24M>;
clock-output-names = "ths";
};
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
reg = <0x01c20140 0x4>;
clocks = <&pll2 SUN4I_A10_PLL2_1X>;
clock-output-names = "codec";
};
};
soc {
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
reg-names = "emac", "syscon";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ahb_rst 17>, <&ahb_rst 66>;
resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
reset-names = "ahb", "ephy";
clocks = <&bus_gates 17>, <&bus_gates 128>;
clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
clock-names = "ahb", "ephy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 96>;
resets = <&apb2_rst 0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 97>;
resets = <&apb2_rst 1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 98>;
resets = <&apb2_rst 2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
r_i2c: i2c@1f02400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01f02400 0x400>;
@ -129,44 +67,29 @@
compatible = "allwinner,sun8i-h3-ts";
reg = <0x01c25000 0x400>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 72>, <&ths_clk>;
clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
clock-names = "ahb", "ths";
resets = <&apb1_rst 8>;
resets = <&ccu RST_BUS_THS 8>;
#thermal-sensor-cells = <0>;
};
dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-h3-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 6>;
clock-names = "ahb";
resets = <&ahb_rst 6>;
reset-names = "ahb";
#dma-cells = <1>;
};
codec: codec@01c22c00 {
compatible = "allwinner,sun8i-h3-codec";
reg = <0x01c22c00 0x100>, <0x01f015c0 0x4>;
reg-names = "codec", "pr";
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 64>, <&codec_clk>;
clock-names = "ahb", "codec";
resets = <&ahb_rst 128>;
reset-names = "ahb";
dmas = <&dma 15>, <&dma 15>;
dma-names = "rx", "tx";
status = "disabled";
};
/* codec: codec@01c22c00 { */
/* compatible = "allwinner,sun8i-h3-codec"; */
/* reg = <0x01c22c00 0x100>, <0x01f015c0 0x4>; */
/* reg-names = "codec", "pr"; */
/* interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; */
/* clocks = <&ccu CLK_BUS_CODEC>, <&codec_clk>; */
/* clock-names = "ahb", "codec"; */
/* resets = <&ahb_rst 128>; */
/* reset-names = "ahb"; */
/* dmas = <&dma 15>, <&dma 15>; */
/* dma-names = "rx", "tx"; */
/* status = "disabled"; */
/* }; */
};
};
&pll1 {
compatible = "allwinner,sun8i-h3-pll1-clk";
};
&pio {
emac_pins_rgmii_a: emac_rgmii@0 {
allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
@ -176,4 +99,11 @@
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
emac_phy_reset_pin: emac_phy_reset_pin@0 {
allwinner,pins = "PD6";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};

12
sys/boot/fdt/dts/arm/orangepi-plus-2e.dts
View File

@ -101,12 +101,12 @@
};
};
&codec {
pinctrl-names = "default";
pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
status = "okay";
};
/* &codec { */
/* pinctrl-names = "default"; */
/* pinctrl-0 = <&codec_pa_pin>; */
/* allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /\* PA16 *\/ */
/* status = "okay"; */
/* }; */
&cpu0 {
cpu-supply = <&vdd_cpu>;