Fill out some gaps in ia64 DDB support. This involves generalising DDB's
breakpoint handling slightly to cope with the fact that ia64 instructions are not located on byte boundaries.
This commit is contained in:
parent
de1792cbb8
commit
3a0b4f259c
@ -48,6 +48,8 @@ extern db_regs_t ddb_regs; /* register state */
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#define BKPT_SIZE (1) /* size of breakpoint inst */
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#define BKPT_SET(inst) (BKPT_INST)
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#define BKPT_SKIP ddb_regs.tf_eip += 1
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#define FIXUP_PC_AFTER_BREAK ddb_regs.tf_eip -= 1;
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#define db_clear_single_step(regs) ((regs)->tf_eflags &= ~PSL_T)
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@ -165,6 +165,19 @@ db_find_breakpoint_here(addr)
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static boolean_t db_breakpoints_inserted = TRUE;
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#ifndef BKPT_WRITE
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#define BKPT_WRITE(addr, storage) \
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do { \
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*storage = db_get_value(addr, BKPT_SIZE, FALSE); \
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db_put_value(addr, BKPT_SIZE, BKPT_SET(*storage)); \
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} while (0)
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#endif
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#ifndef BKPT_CLEAR
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#define BKPT_CLEAR(addr, storage) \
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db_put_value(addr, BKPT_SIZE, *storage)
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#endif
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void
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db_set_breakpoints()
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{
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@ -172,18 +185,13 @@ db_set_breakpoints()
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if (!db_breakpoints_inserted) {
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for (bkpt = db_breakpoint_list;
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bkpt != 0;
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bkpt = bkpt->link)
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if (db_map_current(bkpt->map)) {
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bkpt->bkpt_inst = db_get_value(bkpt->address,
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BKPT_SIZE,
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FALSE);
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db_put_value(bkpt->address,
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BKPT_SIZE,
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BKPT_SET(bkpt->bkpt_inst));
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}
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db_breakpoints_inserted = TRUE;
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for (bkpt = db_breakpoint_list;
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bkpt != 0;
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bkpt = bkpt->link)
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if (db_map_current(bkpt->map)) {
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BKPT_WRITE(bkpt->address, &bkpt->bkpt_inst);
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}
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db_breakpoints_inserted = TRUE;
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}
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}
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@ -194,13 +202,13 @@ db_clear_breakpoints()
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if (db_breakpoints_inserted) {
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for (bkpt = db_breakpoint_list;
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bkpt != 0;
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bkpt = bkpt->link)
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if (db_map_current(bkpt->map)) {
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db_put_value(bkpt->address, BKPT_SIZE, bkpt->bkpt_inst);
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}
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db_breakpoints_inserted = FALSE;
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for (bkpt = db_breakpoint_list;
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bkpt != 0;
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bkpt = bkpt->link)
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if (db_map_current(bkpt->map)) {
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BKPT_CLEAR(bkpt->address, &bkpt->bkpt_inst);
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}
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db_breakpoints_inserted = FALSE;
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}
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}
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@ -228,8 +236,7 @@ db_set_temp_breakpoint(addr)
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bkpt->init_count = 1;
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bkpt->count = 1;
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bkpt->bkpt_inst = db_get_value(bkpt->address, BKPT_SIZE, FALSE);
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db_put_value(bkpt->address, BKPT_SIZE, BKPT_SET(bkpt->bkpt_inst));
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BKPT_WRITE(bkpt->address, &bkpt->bkpt_inst);
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return bkpt;
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}
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@ -237,7 +244,7 @@ void
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db_delete_temp_breakpoint(bkpt)
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db_breakpoint_t bkpt;
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{
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db_put_value(bkpt->address, BKPT_SIZE, bkpt->bkpt_inst);
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BKPT_CLEAR(bkpt->address, &bkpt->bkpt_inst);
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db_breakpoint_free(bkpt);
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}
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#endif /* SOFTWARE_SSTEP */
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@ -37,6 +37,10 @@
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* Breakpoint.
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*/
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#ifndef BKPT_INST_TYPE
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#define BKPT_INST_TYPE int
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#endif
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struct db_breakpoint {
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vm_map_t map; /* in this map */
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db_addr_t address; /* set here */
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@ -45,7 +49,7 @@ struct db_breakpoint {
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int flags; /* flags: */
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#define BKPT_SINGLE_STEP 0x2 /* to simulate single step */
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#define BKPT_TEMP 0x4 /* temporary */
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int bkpt_inst; /* saved instruction at bkpt */
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BKPT_INST_TYPE bkpt_inst; /* saved instruction at bkpt */
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struct db_breakpoint *link; /* link in in-use or free chain */
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};
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typedef struct db_breakpoint *db_breakpoint_t;
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@ -104,8 +104,8 @@ db_stop_at_pc(is_breakpoint)
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return (TRUE); /* stop here */
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}
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} else if (*is_breakpoint) {
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#ifdef __i386__ /* XXx */
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ddb_regs.tf_eip += 1;
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#ifdef BKPT_SKIP
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BKPT_SKIP;
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#endif
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}
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@ -48,6 +48,8 @@ extern db_regs_t ddb_regs; /* register state */
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#define BKPT_SIZE (1) /* size of breakpoint inst */
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#define BKPT_SET(inst) (BKPT_INST)
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#define BKPT_SKIP ddb_regs.tf_eip += 1
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#define FIXUP_PC_AFTER_BREAK ddb_regs.tf_eip -= 1;
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#define db_clear_single_step(regs) ((regs)->tf_eflags &= ~PSL_T)
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@ -39,11 +39,6 @@
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#define sign_extend(imm, w) (((int64_t)(imm) << (64 - (w))) >> (64 - (w)))
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struct ia64_bundle {
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u_int64_t slot[3];
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int template;
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};
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typedef void (*ia64_print_slot)(db_addr_t loc, u_int64_t slot, boolean_t showregs);
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static void ia64_print_M(db_addr_t, u_int64_t, boolean_t);
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@ -252,20 +247,6 @@ const char *control_names[] = {
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"cr124", "cr125", "cr126", "cr127",
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};
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static void
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ia64_fetch_bundle(db_addr_t loc, struct ia64_bundle *bp)
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{
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u_int64_t low, high;
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db_read_bytes(loc, 8, (caddr_t) &low);
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db_read_bytes(loc+8, 8, (caddr_t) &high);
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bp->template = low & 0x1f;
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bp->slot[0] = (low >> 5) & ((1L<<41) - 1);
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bp->slot[1] = (low >> 46) | ((high & ((1L<<23) - 1)) << 18);
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bp->slot[2] = (high >> 23);
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}
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static void
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ia64_print_ill(const char *name, u_int64_t ins, db_addr_t loc)
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{
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@ -1640,7 +1621,7 @@ ia64_print_X1(const char *name, u_int64_t ins, db_addr_t loc)
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struct ia64_bundle b;
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union ia64_instruction u;
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u.ins = ins;
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ia64_fetch_bundle(loc, &b);
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db_read_bundle(loc, &b);
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db_printf("%s %lx",
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name,
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(b.slot[1] << 21) | (u.X1.i << 20) | u.X1.imm20a);
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@ -1652,7 +1633,7 @@ ia64_print_X2(const char *name, u_int64_t ins, db_addr_t loc)
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struct ia64_bundle b;
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union ia64_instruction u;
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u.ins = ins;
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ia64_fetch_bundle(loc, &b);
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db_read_bundle(loc, &b);
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db_printf("%s %s=%lx",
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name,
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register_names[u.X2.r1],
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@ -2848,7 +2829,7 @@ db_disasm(db_addr_t loc, boolean_t altfmt)
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*/
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slot = loc & 15;
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loc &= ~15;
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ia64_fetch_bundle(loc, &b);
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db_read_bundle(loc, &b);
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if (b.slot[slot] & 63)
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db_printf("(p%ld) ", b.slot[slot] & 63);
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@ -75,11 +75,13 @@ extern int trap_types;
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int db_active;
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static u_int64_t zero;
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static int db_get_rse_reg(struct db_variable *vp, db_expr_t *valuep, int op);
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static int db_get_pc_reg(struct db_variable *vp, db_expr_t *valuep, int op);
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struct db_variable db_regs[] = {
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/* Misc control/app registers */
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#define DB_MISC_REGS 14 /* make sure this is correct */
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#define DB_MISC_REGS 15 /* make sure this is correct */
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{"pc", (db_expr_t*) 0, db_get_pc_reg},
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{"ip", (db_expr_t*) &ddb_regs.tf_cr_iip, FCN_NULL},
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{"psr", (db_expr_t*) &ddb_regs.tf_cr_ipsr, FCN_NULL},
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{"cr.isr", (db_expr_t*) &ddb_regs.tf_cr_isr, FCN_NULL},
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@ -295,6 +297,14 @@ db_get_rse_reg(struct db_variable *vp, db_expr_t *valuep, int op)
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return 0;
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}
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static int
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db_get_pc_reg(struct db_variable *vp, db_expr_t *valuep, int op)
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{
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/* Read only */
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if (op == DB_VAR_GET)
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*valuep = PC_REGS(DDB_REGS);
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}
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/*
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* Print trap reason.
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*/
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@ -323,7 +333,8 @@ kdb_trap(int vector, struct trapframe *regs)
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* conditions exist, something Bad has happened.
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*/
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if (vector != IA64_VEC_BREAK) {
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if (vector != IA64_VEC_BREAK
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&& vector != IA64_VEC_SINGLE_STEP_TRAP) {
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#if 0
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if (ddb_mode) {
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db_printf("ddbprinttrap from 0x%lx\n", /* XXX */
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@ -466,3 +477,69 @@ db_register_value(regs, regno)
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}
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}
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}
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void
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db_read_bundle(db_addr_t addr, struct ia64_bundle *bp)
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{
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u_int64_t low, high;
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db_read_bytes(addr, 8, (caddr_t) &low);
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db_read_bytes(addr+8, 8, (caddr_t) &high);
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bp->template = low & 0x1f;
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bp->slot[0] = (low >> 5) & ((1L<<41) - 1);
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bp->slot[1] = (low >> 46) | ((high & ((1L<<23) - 1)) << 18);
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bp->slot[2] = (high >> 23);
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}
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void
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db_write_bundle(db_addr_t addr, struct ia64_bundle *bp)
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{
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u_int64_t low, high;
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low = bp->template | (bp->slot[0] << 5) | (bp->slot[1] << 46);
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high = (bp->slot[1] >> 18) | (bp->slot[2] << 23);
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db_write_bytes(addr, 8, (caddr_t) &low);
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db_write_bytes(addr+8, 8, (caddr_t) &high);
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}
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void
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db_write_breakpoint(vm_offset_t addr, u_int64_t *storage)
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{
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struct ia64_bundle b;
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int slot;
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slot = addr & 15;
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addr &= ~15;
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db_read_bundle(addr, &b);
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*storage = b.slot[slot];
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b.slot[slot] = 0x80100 << 6; /* break.* 0x80100 */
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db_write_bundle(addr, &b);
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}
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void
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db_clear_breakpoint(vm_offset_t addr, u_int64_t *storage)
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{
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struct ia64_bundle b;
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int slot;
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slot = addr & 15;
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addr &= ~15;
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db_read_bundle(addr, &b);
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b.slot[slot] = *storage;
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db_write_bundle(addr, &b);
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}
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void
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db_skip_breakpoint(void)
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{
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/*
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* Skip past the break instruction.
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*/
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ddb_regs.tf_cr_ipsr += IA64_PSR_RI_1;
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if ((ddb_regs.tf_cr_ipsr & IA64_PSR_RI) > IA64_PSR_RI_2) {
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ddb_regs.tf_cr_ipsr &= ~IA64_PSR_RI;
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ddb_regs.tf_cr_iip += 16;
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}
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}
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@ -243,9 +243,6 @@ trap(int vector, int imm, struct trapframe *framep)
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/* Always fatal in kernel. Should never happen. */
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goto dopanic;
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case IA64_VEC_BREAK:
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goto dopanic;
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case IA64_VEC_DISABLED_FP:
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/*
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* on exit from the kernel, if thread == fpcurthread,
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@ -394,6 +391,37 @@ trap(int vector, int imm, struct trapframe *framep)
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printtrap(vector, imm, framep, 1, user);
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#endif
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break;
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case IA64_VEC_SINGLE_STEP_TRAP:
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/*
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* Clear single-step bit.
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*/
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framep->tf_cr_ipsr &= IA64_PSR_SS;
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/* FALLTHROUTH */
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case IA64_VEC_DEBUG:
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case IA64_VEC_TAKEN_BRANCH_TRAP:
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case IA64_VEC_BREAK:
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/*
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* These are always fatal in kernel, and should never happen.
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*/
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if (!user) {
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#ifdef DDB
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/*
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* ...unless, of course, DDB is configured.
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*/
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if (kdb_trap(vector, framep))
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return;
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/*
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* If we get here, DDB did _not_ handle the
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* trap, and we need to PANIC!
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*/
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#endif
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goto dopanic;
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}
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i = SIGTRAP;
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break;
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}
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default:
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#define DB_NO_AOUT
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struct ia64_bundle {
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u_int64_t slot[3];
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int template;
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};
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typedef vm_offset_t db_addr_t; /* address - unsigned */
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typedef long db_expr_t; /* expression - signed */
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typedef struct trapframe db_regs_t;
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@ -50,16 +55,16 @@ db_regs_t ddb_regs; /* register state */
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#define PC_REGS(regs) ((db_addr_t)(regs)->tf_cr_iip \
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+ (((regs)->tf_cr_ipsr >> 41) & 3))
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#define BKPT_INST 0x00000080 /* breakpoint instruction */
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#define BKPT_SIZE (4) /* size of breakpoint inst */
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#define BKPT_SET(inst) (BKPT_INST)
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#define BKPT_WRITE(addr, storage) db_write_breakpoint(addr, storage)
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#define BKPT_CLEAR(addr, storage) db_clear_breakpoint(addr, storage)
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#define BKPT_INST_TYPE u_int64_t
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#define FIXUP_PC_AFTER_BREAK
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#define BKPT_SKIP db_skip_breakpoint()
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#define db_clear_single_step(regs) 0
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#define db_set_single_step(regs) 0
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#define db_clear_single_step(regs) ddb_regs.tf_cr_ipsr &= ~IA64_PSR_SS
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#define db_set_single_step(regs) ddb_regs.tf_cr_ipsr |= IA64_PSR_SS
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#define IS_BREAKPOINT_TRAP(type, code) 0
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#define IS_BREAKPOINT_TRAP(type, code) (type == IA64_VEC_BREAK)
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#define IS_WATCHPOINT_TRAP(type, code) 0
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#define inst_trap_return(ins) 0
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@ -86,6 +91,12 @@ u_int64_t *db_rse_current_frame(void);
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u_int64_t *db_rse_previous_frame(u_int64_t *bsp, int sof);
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u_int64_t *db_rse_register_address(u_int64_t *bsp, int regno);
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void db_read_bundle(db_addr_t addr, struct ia64_bundle *bp);
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void db_write_bundle(db_addr_t addr, struct ia64_bundle *bp);
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void db_write_breakpoint(db_addr_t addr, u_int64_t *storage);
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void db_clear_breakpoint(db_addr_t addr, u_int64_t *storage);
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void db_skip_breakpoint(void);
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/*
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* Pretty arbitrary
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*/
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