Add a driver for the imx6 on-chip realtime clock.
This driver is standard rather than optional because it can always provide time after a reboot, but it will only provide time after a power cycle if battery power is supplied to the chip's SNVS power domain.
This commit is contained in:
Ian Lepore
parent
1698cbd919
commit
3a28d1b6e3
@ -14,6 +14,7 @@ arm/freescale/imx/imx6_ccm.c standard
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arm/freescale/imx/imx6_machdep.c standard
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arm/freescale/imx/imx6_mp.c optional smp
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arm/freescale/imx/imx6_pl310.c standard
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arm/freescale/imx/imx6_snvs.c standard
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arm/freescale/imx/imx6_src.c standard
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arm/freescale/imx/imx_epit.c standard
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arm/freescale/imx/imx_iomux.c standard
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228
sys/arm/freescale/imx/imx6_snvs.c
Normal file
228
sys/arm/freescale/imx/imx6_snvs.c
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@ -0,0 +1,228 @@
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/*-
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* Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for imx6 Secure Non-Volatile Storage system, which really means "all
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* the stuff that's powered by a battery when main power is off". This includes
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* realtime clock, tamper monitor, and power-management functions. Currently
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* this driver provides only realtime clock support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "clock_if.h"
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#define SNVS_LPCR 0x38 /* Control register */
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#define LPCR_LPCALB_VAL_SHIFT 10 /* Calibration shift */
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#define LPCR_LPCALB_VAL_MASK 0x1f /* Calibration mask */
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#define LPCR_LPCALB_EN (1u << 8) /* Calibration enable */
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#define LPCR_SRTC_ENV (1u << 0) /* RTC enabled/valid */
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#define SNVS_LPSRTCMR 0x50 /* Counter MSB */
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#define SNVS_LPSRTCLR 0x54 /* Counter LSB */
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#define RTC_RESOLUTION_US (1000000 / 32768) /* 32khz clock */
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/*
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* The RTC is a 47-bit counter clocked at 32KHz and organized as a 32.15
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* fixed-point binary value. Shifting by SBT_LSB bits translates between
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* counter and sbintime values.
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*/
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#define RTC_BITS 47
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#define SBT_BITS 64
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#define SBT_LSB (SBT_BITS - RTC_BITS)
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struct snvs_softc {
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device_t dev;
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struct resource * memres;
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uint32_t lpcr;
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};
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static struct ofw_compat_data compat_data[] = {
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{"fsl,sec-v4.0-mon", true},
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{NULL, false}
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};
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static inline uint32_t
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RD4(struct snvs_softc *sc, bus_size_t offset)
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{
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return (bus_read_4(sc->memres, offset));
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}
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static inline void
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WR4(struct snvs_softc *sc, bus_size_t offset, uint32_t value)
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{
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bus_write_4(sc->memres, offset, value);
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}
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static void
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snvs_rtc_enable(struct snvs_softc *sc, bool enable)
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{
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uint32_t enbit;
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if (enable)
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sc->lpcr |= LPCR_SRTC_ENV;
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else
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sc->lpcr &= ~LPCR_SRTC_ENV;
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WR4(sc, SNVS_LPCR, sc->lpcr);
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/* Wait for the hardware to achieve the requested state. */
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enbit = sc->lpcr & LPCR_SRTC_ENV;
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while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit)
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continue;
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}
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static int
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snvs_gettime(device_t dev, struct timespec *ts)
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{
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struct snvs_softc *sc;
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sbintime_t counter1, counter2;
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sc = device_get_softc(dev);
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/* If the clock is not enabled and valid, we can't help. */
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if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) {
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return (EINVAL);
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}
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/*
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* The counter is clocked asynchronously to cpu accesses; read and
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* assemble the pieces of the counter until we get the same value twice.
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* The counter is 47 bits, organized as a 32.15 binary fixed-point
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* value. If we shift it up to the high order part of a 64-bit word it
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* turns into an sbintime.
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*/
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do {
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counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
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counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
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counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
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counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
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} while (counter1 != counter2);
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*ts = sbttots(counter1);
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return (0);
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}
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static int
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snvs_settime(device_t dev, struct timespec *unused)
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{
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struct snvs_softc *sc;
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struct bintime bt;
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sbintime_t sbt;
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sc = device_get_softc(dev);
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/*
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* Ignore the inaccurate time passed in from the common clock code and
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* obtain a time worthy of our 30us accuracy.
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*/
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bintime(&bt);
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bt.sec -= utc_offset();
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sbt = bttosbt(bt);
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/*
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* It takes two clock cycles for the counter to start after setting the
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* enable bit, so add two SBT_LSBs to what we're about to set.
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*/
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sbt += 2 << SBT_LSB;
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snvs_rtc_enable(sc, false);
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WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32)));
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WR4(sc, SNVS_LPSRTCLR, (uint32_t)(sbt >> (SBT_LSB)));
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snvs_rtc_enable(sc, true);
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return (0);
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}
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static int
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snvs_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "i.MX6 SNVS RTC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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snvs_attach(device_t dev)
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{
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struct snvs_softc *sc;
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int rid;
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sc = device_get_softc(dev);
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sc->dev = dev;
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rid = 0;
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sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->memres == NULL) {
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device_printf(sc->dev, "could not allocate registers\n");
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return (ENXIO);
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}
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clock_register(sc->dev, RTC_RESOLUTION_US);
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return (0);
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}
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static device_method_t snvs_methods[] = {
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DEVMETHOD(device_probe, snvs_probe),
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DEVMETHOD(device_attach, snvs_attach),
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/* clock_if methods */
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DEVMETHOD(clock_gettime, snvs_gettime),
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DEVMETHOD(clock_settime, snvs_settime),
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DEVMETHOD_END
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};
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static driver_t snvs_driver = {
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"snvs",
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snvs_methods,
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sizeof(struct snvs_softc),
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};
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static devclass_t snvs_devclass;
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DRIVER_MODULE(snvs, simplebus, snvs_driver, snvs_devclass, 0, 0);
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