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arge: do a read-after-write on all arge register writes, not just MDIO writes.

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This flushes out the write to the system before anything continues.

The mips74k guide, chapter 3.3.3 (write gathering) notes that writes
can be buffered in FIFOs - even uncached ones - so we can't guarantee
the device has felt its effects.  Now, since we're all lazy driver
authors and don't pepper read/write barriers everywhere, fake it here.

tested:

* mips74k - QCA9558 SoC (AP135 reference board)
This commit is contained in:
Adrian Chadd 2015-10-30 22:53:30 +00:00
parent ca8d93fc70
commit 3b8a3b85eb
1 changed files with 2 additions and 4 deletions
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6
sys/mips/atheros/if_argevar.h
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@ -68,6 +68,7 @@
#define ARGE_WRITE(sc, reg, val) do { \
bus_write_4(sc->arge_res, (reg), (val)); \
ARGE_BARRIER_WRITE((sc)); \
ARGE_READ((sc), (reg)); \
} while (0)
#define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg))
@ -87,10 +88,7 @@
* FIFO(s) before we continue issuing MDIO bus updates.
*/
#define ARGE_MDIO_WRITE(_sc, _reg, _val) \
do { \
ARGE_WRITE((_sc), (_reg), (_val)); \
ARGE_READ((_sc), (_reg)); \
} while (0)
ARGE_WRITE((_sc), (_reg), (_val))
#define ARGE_MDIO_READ(_sc, _reg) \
ARGE_READ((_sc), (_reg))
#define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc)