Fully disable interrupts while we fiddle with the FP context in the
VIS-based block copy/zero implementations. While with 4BSD it's sufficient to just disable the tick interrupts, with ULE+PREEMPTION it's otherwise also possible that these are preempted via IPIs.
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@ -580,8 +580,8 @@ fpu_fault_begin:
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* void spitfire_block_copy(void *src, void *dst, size_t len)
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*/
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ENTRY(spitfire_block_copy)
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rdpr %pil, %o3
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wrpr %g0, PIL_TICK, %pil
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rdpr %pstate, %o3
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wrpr %g0, PSTATE_NORMAL, %pstate
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wr %g0, ASI_BLK_S, %asi
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wr %g0, FPRS_FEF, %fprs
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@ -603,7 +603,7 @@ ENTRY(spitfire_block_copy)
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or %o4, PCB_FEF, %o4
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stx %o4, [PCB_REG + PCB_FLAGS]
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1: wrpr %o3, 0, %pil
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1: wrpr %o3, 0, %pstate
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ldda [%o0] %asi, %f0
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add %o0, 64, %o0
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@ -653,8 +653,8 @@ END(spitfire_block_copy)
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ENTRY(zeus_block_copy)
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prefetch [%o0 + (0 * 64)], 0
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rdpr %pil, %o3
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wrpr %g0, PIL_TICK, %pil
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rdpr %pstate, %o3
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wrpr %g0, PSTATE_NORMAL, %pstate
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wr %g0, ASI_BLK_S, %asi
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wr %g0, FPRS_FEF, %fprs
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@ -676,7 +676,7 @@ ENTRY(zeus_block_copy)
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or %o4, PCB_FEF, %o4
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stx %o4, [PCB_REG + PCB_FLAGS]
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1: wrpr %o3, 0, %pil
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1: wrpr %o3, 0, %pstate
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ldd [%o0 + (0 * 8)], %f0
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prefetch [%o0 + (1 * 64)], 0
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@ -764,8 +764,8 @@ END(zeus_block_copy)
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*/
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ALTENTRY(zeus_block_zero)
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ENTRY(spitfire_block_zero)
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rdpr %pil, %o3
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wrpr %g0, PIL_TICK, %pil
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rdpr %pstate, %o3
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wrpr %g0, PSTATE_NORMAL, %pstate
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wr %g0, ASI_BLK_S, %asi
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wr %g0, FPRS_FEF, %fprs
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@ -787,7 +787,7 @@ ENTRY(spitfire_block_zero)
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or %o4, PCB_FEF, %o4
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stx %o4, [PCB_REG + PCB_FLAGS]
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1: wrpr %o3, 0, %pil
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1: wrpr %o3, 0, %pstate
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fzero %f0
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fzero %f2
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