powerpc/SPE: Reload vector registers after efdabs/efdnabs/efdneg

While here, also style(9)-adjust indents around this code.
This commit is contained in:
Justin Hibbits 2018-12-09 04:13:14 +00:00
parent 470b28812f
commit 3d6bebd3a2

View File

@ -464,17 +464,17 @@ spe_handle_fpdata(struct trapframe *frame)
switch (instr_sec_op) { switch (instr_sec_op) {
case EVFSABS: case EVFSABS:
curthread->td_pcb->pcb_vec.vr[rd][0] = curthread->td_pcb->pcb_vec.vr[rd][0] =
curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31); curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31);
frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31); frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31);
break; break;
case EVFSNABS: case EVFSNABS:
curthread->td_pcb->pcb_vec.vr[rd][0] = curthread->td_pcb->pcb_vec.vr[rd][0] =
curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31); curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31);
frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31); frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31);
break; break;
case EVFSNEG: case EVFSNEG:
curthread->td_pcb->pcb_vec.vr[rd][0] = curthread->td_pcb->pcb_vec.vr[rd][0] =
curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31); curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31);
frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31); frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
break; break;
default: default:
@ -542,15 +542,18 @@ spe_handle_fpdata(struct trapframe *frame)
switch (instr_sec_op) { switch (instr_sec_op) {
case EFDABS: case EFDABS:
curthread->td_pcb->pcb_vec.vr[rd][0] = curthread->td_pcb->pcb_vec.vr[rd][0] =
curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31); curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31);
enable_vec(curthread);
break; break;
case EFDNABS: case EFDNABS:
curthread->td_pcb->pcb_vec.vr[rd][0] = curthread->td_pcb->pcb_vec.vr[rd][0] =
curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31); curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31);
enable_vec(curthread);
break; break;
case EFDNEG: case EFDNEG:
curthread->td_pcb->pcb_vec.vr[rd][0] = curthread->td_pcb->pcb_vec.vr[rd][0] =
curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31); curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31);
enable_vec(curthread);
break; break;
case EFDCFS: case EFDCFS:
spe_explode(&fpemu, &fpemu.fe_f3, SINGLE, spe_explode(&fpemu, &fpemu.fe_f3, SINGLE,