powerpc/SPE: Reload vector registers after efdabs/efdnabs/efdneg
While here, also style(9)-adjust indents around this code.
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470b28812f
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3d6bebd3a2
@ -464,17 +464,17 @@ spe_handle_fpdata(struct trapframe *frame)
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switch (instr_sec_op) {
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switch (instr_sec_op) {
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case EVFSABS:
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case EVFSABS:
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31);
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curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31);
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frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31);
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frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31);
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break;
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break;
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case EVFSNABS:
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case EVFSNABS:
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31);
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curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31);
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frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31);
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frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31);
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break;
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break;
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case EVFSNEG:
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case EVFSNEG:
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31);
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curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31);
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frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
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frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
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break;
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break;
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default:
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default:
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@ -542,15 +542,18 @@ spe_handle_fpdata(struct trapframe *frame)
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switch (instr_sec_op) {
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switch (instr_sec_op) {
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case EFDABS:
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case EFDABS:
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31);
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curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31);
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enable_vec(curthread);
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break;
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break;
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case EFDNABS:
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case EFDNABS:
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31);
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curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31);
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enable_vec(curthread);
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break;
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break;
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case EFDNEG:
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case EFDNEG:
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[rd][0] =
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curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31);
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curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31);
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enable_vec(curthread);
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break;
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break;
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case EFDCFS:
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case EFDCFS:
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spe_explode(&fpemu, &fpemu.fe_f3, SINGLE,
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spe_explode(&fpemu, &fpemu.fe_f3, SINGLE,
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