Does 4 things:

1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
   intr_machdep.c.  This allows us to have an architecture dependant intr_machdep.c
   (which we will need for RMI) in the machine specific directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
   may need to look at finding a better place to put this. But first I want to
   get this thing compiling.

sys/conf/files.mips

@@ -64,7 +64,6 @@ mips/mips/db_interface.c	optional	ddb
 mips/mips/db_trace.c		optional	ddb
 mips/mips/dump_machdep.c	standard
 mips/mips/in_cksum.c		optional	inet
-mips/mips/intr_machdep.c	standard
 mips/mips/locore.S		standard	no-obj
 mips/mips/mem.c			optional	mem
 mips/mips/nexus.c		standard

sys/mips/adm5120/files.adm5120

@@ -9,3 +9,4 @@ mips/adm5120/obio.c		standard
 mips/adm5120/uart_bus_adm5120.c	optional uart
 mips/adm5120/uart_cpu_adm5120.c	optional uart
 mips/adm5120/uart_dev_adm5120.c	optional uart
+mips/mips/intr_machdep.c        standard

sys/mips/alchemy/files.alchemy

@@ -5,3 +5,4 @@ mips/alchemy/alchemy_machdep.c	standard
 mips/alchemy/obio.c		standard
 mips/alchemy/uart_bus_alchemy.c	optional uart
 mips/alchemy/uart_cpu_alchemy.c	optional uart
+mips/mips/intr_machdep.c        standard

sys/mips/atheros/files.ar71xx

@@ -12,3 +12,4 @@ mips/atheros/if_arge.c		optional arge
 mips/atheros/uart_bus_ar71xx.c	optional uart
 mips/atheros/uart_cpu_ar71xx.c	optional uart
 mips/atheros/ar71xx_bus_space_reversed.c	standard
+mips/mips/intr_machdep.c        standard

sys/mips/idt/files.idt

@@ -6,3 +6,4 @@ mips/idt/if_kr.c		optional kr
 mips/idt/obio.c			standard
 mips/idt/uart_cpu_rc32434.c	optional uart
 mips/idt/uart_bus_rc32434.c	optional uart
+mips/mips/intr_machdep.c        standard

sys/mips/include/intr_machdep.h

@@ -29,8 +29,26 @@
 #ifndef	_MACHINE_INTR_MACHDEP_H_
 #define	_MACHINE_INTR_MACHDEP_H_
 
+#ifdef TARGET_XLR_XLS
+/*
+ * XLR/XLS uses its own intr_machdep.c and has
+ * a different number of interupts. This probably
+ * should be placed somewhere else.
+ */
+
+struct mips_intrhand {
+        struct  intr_event *mih_event;
+        driver_intr_t      *mih_disable;
+        volatile long       *cntp;  /* interrupt counter */
+};
+
+extern struct mips_intrhand mips_intr_handlers[];
+#define XLR_MAX_INTR 64 
+
+#else
 #define NHARD_IRQS	6
 #define NSOFT_IRQS	2
+#endif
 
 struct trapframe;
 
@@ -40,4 +58,5 @@ void cpu_establish_softintr(const char *, int (*)(void*), void (*)(void*),
     void *, int, int, void **);
 void cpu_intr(struct trapframe *);
 
+
 #endif /* !_MACHINE_INTR_MACHDEP_H_ */

sys/mips/malta/files.malta

@@ -7,3 +7,4 @@ mips/malta/uart_bus_maltausart.c	optional uart
 dev/uart/uart_dev_ns8250.c		optional uart
 mips/malta/malta_machdep.c		standard
 mips/malta/yamon.c			standard
+mips/mips/intr_machdep.c		standard

sys/mips/octeon1/files.octeon1

@@ -13,3 +13,4 @@ mips/octeon1/octeon_machdep.c			standard
 mips/octeon1/uart_bus_octeonusart.c		optional uart
 mips/octeon1/uart_cpu_octeonusart.c		optional uart
 mips/octeon1/uart_dev_oct16550.c		optional uart
+mips/mips/intr_machdep.c			standard

sys/mips/sentry5/files.sentry5

@@ -5,3 +5,4 @@
 # which are believed to be devices we have drivers for
 # which just need to be tweaked for attachment to an SSB system bus.
 mips/sentry5/s5_machdep.c		standard
+mips/mips/intr_machdep.c		standard

sys/mips/sibyte/files.sibyte

@@ -5,5 +5,5 @@ mips/sibyte/sb_zbbus.c				standard
 mips/sibyte/sb_zbpci.c				standard
 mips/sibyte/sb_scd.c				standard
 mips/sibyte/ata_zbbus.c				standard
-
+mips/mips/intr_machdep.c			standard
 mips/sibyte/sb_asm.S				standard