- Make PCI_QUIRK_MSI_INTX_BUG work by using the ID of the actual PCI device
for the lookup. - For devices affected by PCI_QUIRK_MSI_INTX_BUG, ensure PCIM_CMD_INTxDIS is cleared when using MSI/MSI-X. - Employ PCI_QUIRK_MSI_INTX_BUG for BCM5714(S)/BCM5715(S)/BCM5780(S) rather than clearing PCIM_CMD_INTxDIS unconditionally for all devices in bge(4). MFC after: 3 days
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@ -1946,11 +1946,9 @@ bge_chipinit(struct bge_softc *sc)
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/*
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/*
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* Disable memory write invalidate. Apparently it is not supported
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* Disable memory write invalidate. Apparently it is not supported
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* properly by these devices. Also ensure that INTx isn't disabled,
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* properly by these devices.
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* as these chips need it even when using MSI.
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*/
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*/
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PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
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PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
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PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
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/* Set the timer prescaler (always 66 MHz). */
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/* Set the timer prescaler (always 66 MHz). */
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CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
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CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
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@ -268,7 +268,7 @@ static const struct pci_quirk pci_quirks[] = {
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{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
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{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
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/*
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/*
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* Atheros AR8161/AR8162/E2200 ethernet controller has a bug that
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* Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that
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* MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the
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* MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the
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* command register is set.
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* command register is set.
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*/
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*/
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@ -276,6 +276,17 @@ static const struct pci_quirk pci_quirks[] = {
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{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
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{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
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{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
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{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
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/*
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* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
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* issue MSI interrupts with PCIM_CMD_INTxDIS set either.
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*/
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{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */
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{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */
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{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */
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{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */
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{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */
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{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */
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{ 0 }
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{ 0 }
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};
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};
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@ -3866,14 +3877,16 @@ pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
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mte->mte_handlers++;
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mte->mte_handlers++;
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}
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}
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if (!pci_has_quirk(pci_get_devid(dev),
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PCI_QUIRK_MSI_INTX_BUG)) {
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/*
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/*
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* Make sure that INTx is disabled if we are
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* Make sure that INTx is disabled if we are using MSI/MSI-X,
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* using MSI/MSIX
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* unless the device is affected by PCI_QUIRK_MSI_INTX_BUG,
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* in which case we "enable" INTx so MSI/MSI-X actually works.
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*/
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*/
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if (!pci_has_quirk(pci_get_devid(child),
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PCI_QUIRK_MSI_INTX_BUG))
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pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
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pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
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}
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else
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pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
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bad:
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bad:
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if (error) {
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if (error) {
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(void)bus_generic_teardown_intr(dev, child, irq,
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(void)bus_generic_teardown_intr(dev, child, irq,
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