From 40a7c811129cdb067e21450eb9b58625e4646dbd Mon Sep 17 00:00:00 2001 From: Peter Wemm Date: Thu, 11 Dec 2003 04:47:53 +0000 Subject: [PATCH] CACHE_LINE_SIZE is 64 on athlon and amd64 chips, not 32. This should probably be 128 since that is what the hardware prefetch fill size is on both the p3, p4 and athlon* cpus. --- libexec/rtld-elf/amd64/lockdflt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libexec/rtld-elf/amd64/lockdflt.c b/libexec/rtld-elf/amd64/lockdflt.c index fd74cbaeb8cf..b3b49350bab4 100644 --- a/libexec/rtld-elf/amd64/lockdflt.c +++ b/libexec/rtld-elf/amd64/lockdflt.c @@ -55,7 +55,7 @@ #include "debug.h" #include "rtld.h" -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 64 #define WAFLAG 0x1 /* A writer holds the lock */ #define RC_INCR 0x2 /* Adjusts count of readers desiring lock */