Add driver for Synopsys DesignWare Mobile Storage Host Controller.
Sponsored by: DARPA, AFRL
This commit is contained in:
Ruslan Bukin
parent
8ccb28efcd
commit
41709d23c4
@ -19,3 +19,4 @@ arm/altera/socfpga/socfpga_manager.c standard
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arm/altera/socfpga/socfpga_rstmgr.c standard
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dev/dwc/if_dwc.c optional dwc
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dev/mmc/host/dwmmc.c optional dwmmc
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@ -89,6 +89,9 @@ platform_devmap_init(void)
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*/
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arm_devmap_add_entry(0xffb00000, 0x100000);
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/* dwmmc */
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arm_devmap_add_entry(0xff700000, 0x100000);
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return (0);
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}
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@ -80,7 +80,7 @@ options NFS_ROOT # NFS usable as /, requires NFSCLIENT
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device mmc # mmc/sd bus
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device mmcsd # mmc/sd flash cards
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device sdhci # generic sdhci
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device dwmmc
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options ROOTDEVNAME=\"ufs:/dev/da0\"
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@ -82,7 +82,7 @@ options NFS_ROOT # NFS usable as /, requires NFSCLIENT
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device mmc # mmc/sd bus
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device mmcsd # mmc/sd flash cards
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device sdhci # generic sdhci
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device dwmmc
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options ROOTDEVNAME=\"ufs:/dev/da0\"
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@ -78,6 +78,9 @@ platform_devmap_init(void)
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/* UART */
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arm_devmap_add_entry(0x12C00000, 0x100000);
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/* DWMMC */
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arm_devmap_add_entry(0x12200000, 0x100000);
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return (0);
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}
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@ -33,4 +33,4 @@ arm/samsung/exynos/chrome_ec.c optional chrome_ec_i2c
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arm/samsung/exynos/chrome_ec_spi.c optional chrome_ec_spi
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arm/samsung/exynos/chrome_kb.c optional chrome_kb
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#dev/sdhci/sdhci_fdt.c optional sdhci
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dev/mmc/host/dwmmc.c optional dwmmc
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@ -47,8 +47,19 @@
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status = "okay";
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};
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sdhci@12220000 {
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status = "disabled";
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mmc2: dwmmc@12220000 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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bus-frequency = <50000000>;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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};
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};
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};
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@ -68,5 +68,20 @@
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usbdrd_phy1: phy@12500000 {
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vbus-supply = < 218 >;
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};
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mmc2: dwmmc@12220000 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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bus-frequency = <50000000>;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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};
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};
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};
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};
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@ -81,5 +81,32 @@
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xhci@12400000 {
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status = "okay";
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};
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mmc0: dwmmc@12200000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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reg = <0x12200000 0x10000>;
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interrupts = <107>;
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interrupt-parent = <&GIC>;
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc1: dwmmc@12210000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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reg = <0x12210000 0x10000>;
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interrupts = <108>;
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interrupt-parent = <&GIC>;
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc2: dwmmc@12220000 {
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compatible = "samsung,exynos5420-dw-mshc";
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reg = <0x12220000 0x10000>;
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interrupts = <109>;
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interrupt-parent = <&GIC>;
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fifo-depth = <0x40>;
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status = "disabled";
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};
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};
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};
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@ -55,6 +55,19 @@
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gmac1: ethernet@ff702000 {
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status = "okay";
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};
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mmc: dwmmc@ff704000 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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bus-frequency = <25000000>;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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};
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};
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};
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chosen {
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@ -152,5 +152,14 @@
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phy-mode = "rgmii";
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status = "disabled";
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};
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mmc: dwmmc@ff704000 {
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xff704000 0x1000>;
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interrupts = <171>;
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interrupt-parent = <&GIC>;
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fifo-depth = <0x400>;
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status = "disabled";
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};
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};
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};
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1103
sys/dev/mmc/host/dwmmc.c
Normal file
1103
sys/dev/mmc/host/dwmmc.c
Normal file
File diff suppressed because it is too large
Load Diff
150
sys/dev/mmc/host/dwmmc.h
Normal file
150
sys/dev/mmc/host/dwmmc.h
Normal file
@ -0,0 +1,150 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define SDMMC_CTRL 0x0 /* Control Register */
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#define SDMMC_CTRL_USE_IDMAC (1 << 25) /* Use Internal DMAC */
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#define SDMMC_CTRL_DMA_ENABLE (1 << 5) /* */
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#define SDMMC_CTRL_INT_ENABLE (1 << 4) /* Enable interrupts */
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#define SDMMC_CTRL_DMA_RESET (1 << 2) /* Reset DMA */
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#define SDMMC_CTRL_FIFO_RESET (1 << 1) /* Reset FIFO */
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#define SDMMC_CTRL_RESET (1 << 0) /* Reset SD/MMC controller */
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#define SDMMC_PWREN 0x4 /* Power Enable Register */
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#define SDMMC_PWREN_PE (1 << 0) /* Power On */
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#define SDMMC_CLKDIV 0x8 /* Clock Divider Register */
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#define SDMMC_CLKSRC 0xC /* SD Clock Source Register */
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#define SDMMC_CLKENA 0x10 /* Clock Enable Register */
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#define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
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#define SDMMC_CLKENA_CCLK_EN (1 << 0) /* SD/MMC Enable */
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#define SDMMC_TMOUT 0x14 /* Timeout Register */
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#define SDMMC_CTYPE 0x18 /* Card Type Register */
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#define SDMMC_CTYPE_8BIT (1 << 16)
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#define SDMMC_CTYPE_4BIT (1 << 0)
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#define SDMMC_BLKSIZ 0x1C /* Block Size Register */
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#define SDMMC_BYTCNT 0x20 /* Byte Count Register */
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#define SDMMC_INTMASK 0x24 /* Interrupt Mask Register */
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#define SDMMC_INTMASK_SDIO (1 << 16) /* SDIO Interrupt Enable */
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#define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
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#define SDMMC_INTMASK_ACD (1 << 14) /* Auto command done */
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#define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
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#define SDMMC_INTMASK_HLE (1 << 12) /* Hardware locked write err */
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#define SDMMC_INTMASK_FRUN (1 << 11) /* FIFO underrun/overrun err */
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#define SDMMC_INTMASK_HTO (1 << 10) /* Data starvation by host timeout */
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#define SDMMC_INTMASK_DRT (1 << 9) /* Data read timeout */
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#define SDMMC_INTMASK_RTO (1 << 8) /* Response timeout */
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#define SDMMC_INTMASK_DCRC (1 << 7) /* Data CRC error */
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#define SDMMC_INTMASK_RCRC (1 << 6) /* Response CRC error */
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#define SDMMC_INTMASK_RXDR (1 << 5) /* Receive FIFO data request */
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#define SDMMC_INTMASK_TXDR (1 << 4) /* Transmit FIFO data request */
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#define SDMMC_INTMASK_DTO (1 << 3) /* Data transfer over */
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#define SDMMC_INTMASK_CMD_DONE (1 << 2) /* Command done */
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#define SDMMC_INTMASK_RE (1 << 1) /* Response error */
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#define SDMMC_INTMASK_CD (1 << 0) /* Card Detected */
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#define SDMMC_CMDARG 0x28 /* Command Argument Register */
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#define SDMMC_CMD 0x2C /* Command Register */
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#define SDMMC_CMD_START (1 << 31)
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#define SDMMC_CMD_USE_HOLD_REG (1 << 29)
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#define SDMMC_CMD_UPD_CLK_ONLY (1 << 21) /* Update clk only */
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#define SDMMC_CMD_SEND_INIT (1 << 15) /* Send initialization */
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#define SDMMC_CMD_STOP_ABORT (1 << 14) /* stop current data transfer */
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#define SDMMC_CMD_WAIT_PRVDATA (1 << 13) /* Wait for prev data transfer completion */
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#define SDMMC_CMD_SEND_ASTOP (1 << 12) /* Send stop command at end of data tx/rx */
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#define SDMMC_CMD_MODE_STREAM (1 << 11) /* Stream data transfer */
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#define SDMMC_CMD_DATA_WRITE (1 << 10) /* Write to card */
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#define SDMMC_CMD_DATA_EXP (1 << 9) /* Data transfer expected */
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#define SDMMC_CMD_RESP_CRC (1 << 8) /* Check Response CRC */
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#define SDMMC_CMD_RESP_LONG (1 << 7) /* Long response expected */
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#define SDMMC_CMD_RESP_EXP (1 << 6) /* Response expected */
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#define SDMMC_RESP0 0x30 /* Response Register 0 */
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#define SDMMC_RESP1 0x34 /* Response Register 1 */
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#define SDMMC_RESP2 0x38 /* Response Register 2 */
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#define SDMMC_RESP3 0x3C /* Response Register 3 */
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#define SDMMC_MINTSTS 0x40 /* Masked Interrupt Status Register */
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#define SDMMC_RINTSTS 0x44 /* Raw Interrupt Status Register */
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#define SDMMC_STATUS 0x48 /* Status Register */
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#define SDMMC_STATUS_DATA_BUSY (1 << 9) /* card_data[0] */
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#define SDMMC_FIFOTH 0x4C /* FIFO Threshold Watermark Register */
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#define SDMMC_FIFOTH_MSIZE_S 28 /* Burst size of multiple transaction */
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#define SDMMC_FIFOTH_RXWMARK_S 16 /* FIFO threshold watermark level */
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#define SDMMC_FIFOTH_TXWMARK_S 0 /* FIFO threshold watermark level */
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#define SDMMC_CDETECT 0x50 /* Card Detect Register */
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#define SDMMC_WRTPRT 0x54 /* Write Protect Register */
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#define SDMMC_TCBCNT 0x5C /* Transferred CIU Card Byte Count */
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#define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */
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#define SDMMC_DEBNCE 0x64 /* Debounce Count Register */
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#define SDMMC_USRID 0x68 /* User ID Register */
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#define SDMMC_VERID 0x6C /* Version ID Register */
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#define SDMMC_HCON 0x70 /* Hardware Configuration Register */
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#define SDMMC_UHS_REG 0x74 /* UHS-1 Register */
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#define SDMMC_UHS_REG_DDR (1 << 16) /* DDR mode */
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#define SDMMC_RST_N 0x78 /* Hardware Reset Register */
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#define SDMMC_BMOD 0x80 /* Bus Mode Register */
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#define SDMMC_BMOD_DE (1 << 7) /* IDMAC Enable */
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#define SDMMC_BMOD_FB (1 << 1) /* AHB Master Fixed Burst */
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#define SDMMC_BMOD_SWR (1 << 0) /* Reset DMA */
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#define SDMMC_PLDMND 0x84 /* Poll Demand Register */
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#define SDMMC_DBADDR 0x88 /* Descriptor List Base Address */
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#define SDMMC_IDSTS 0x8C /* Internal DMAC Status Register */
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#define SDMMC_IDINTEN 0x90 /* Internal DMAC Interrupt Enable */
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#define SDMMC_IDINTEN_AI (1 << 9) /* Abnormal Interrupt Summary */
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#define SDMMC_IDINTEN_NI (1 << 8) /* Normal Interrupt Summary */
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#define SDMMC_IDINTEN_CES (1 << 5) /* Card Error Summary */
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#define SDMMC_IDINTEN_DU (1 << 4) /* Descriptor Unavailable */
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#define SDMMC_IDINTEN_FBE (1 << 2) /* Fatal Bus Error */
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#define SDMMC_IDINTEN_RI (1 << 1) /* Receive Interrupt */
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#define SDMMC_IDINTEN_TI (1 << 0) /* Transmit Interrupt */
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#define SDMMC_IDINTEN_MASK (SDMMC_IDINTEN_AI | SDMMC_IDINTEN_NI | SDMMC_IDINTEN_CES | \
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SDMMC_IDINTEN_DU | SDMMC_IDINTEN_FBE | SDMMC_IDINTEN_RI | \
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SDMMC_IDINTEN_TI)
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#define SDMMC_DSCADDR 0x94 /* Current Host Descriptor Address */
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#define SDMMC_BUFADDR 0x98 /* Current Buffer Descriptor Address */
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#define SDMMC_CARDTHRCTL 0x100 /* Card Threshold Control Register */
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#define SDMMC_BACK_END_POWER_R 0x104 /* Back End Power Register */
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#define SDMMC_DATA 0x200 /* Data FIFO Access */
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/* eMMC */
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#define EMMCP_MPSBEGIN0 0x1200 /* */
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#define EMMCP_SEND0 0x1204 /* */
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#define EMMCP_CTRL0 0x120C /* */
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#define MPSCTRL_SECURE_READ_BIT (1 << 7)
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#define MPSCTRL_SECURE_WRITE_BIT (1 << 6)
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#define MPSCTRL_NON_SECURE_READ_BIT (1 << 5)
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#define MPSCTRL_NON_SECURE_WRITE_BIT (1 << 4)
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#define MPSCTRL_USE_FUSE_KEY (1 << 3)
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#define MPSCTRL_ECB_MODE (1 << 2)
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#define MPSCTRL_ENCRYPTION (1 << 1)
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#define MPSCTRL_VALID (1 << 0)
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/* Platform-specific defines */
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#define SDMMC_CLKSEL 0x9C
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#define SDMMC_CLKSEL_SAMPLE_SHIFT 0
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#define SDMMC_CLKSEL_DRIVE_SHIFT 16
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#define SDMMC_CLKSEL_DIVIDER_SHIFT 24
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@ -1773,4 +1773,5 @@ DRIVER_MODULE(mmc, sdhci_imx, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, dwmmc, mmc_driver, mmc_devclass, NULL, NULL);
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