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Add a driver for the Sun GEM (Gigabit) and ERI (100 Mb/s) PCI ethernet

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adaptors, ported from NetBSD.
This commit is contained in:
Thomas Moestl 2002-02-27 17:41:06 +00:00
parent 6b14afdf05
commit 42c1b001f7
4 changed files with 2989 additions and 0 deletions
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2017
sys/dev/gem/if_gem.c Normal file
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sys/dev/gem/if_gem_pci.c Normal file
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/*
* Copyright (C) 2001 Eduardo Horvath.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: NetBSD: if_gem_pci.c,v 1.7 2001/10/18 15:09:15 thorpej Exp
*
* $FreeBSD$
*/
/*
* PCI bindings for Sun GEM ethernet controllers.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/resource.h>
#include <sys/socket.h>
#include <machine/endian.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/ofw_machdep.h>
#include <sys/rman.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include <dev/gem/if_gemreg.h>
#include <dev/gem/if_gemvar.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include "miibus_if.h"
struct gem_pci_softc {
struct gem_softc gsc_gem; /* GEM device */
struct resource *gsc_sres;
int gsc_srid;
struct resource *gsc_ires;
int gsc_irid;
void *gsc_ih;
};
static int gem_pci_probe __P((device_t));
static int gem_pci_attach __P((device_t));
static device_method_t gem_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, gem_pci_probe),
DEVMETHOD(device_attach, gem_pci_attach),
/* bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
/* MII interface */
DEVMETHOD(miibus_readreg, gem_mii_readreg),
DEVMETHOD(miibus_writereg, gem_mii_writereg),
DEVMETHOD(miibus_statchg, gem_mii_statchg),
{ 0, 0 }
};
static driver_t gem_pci_driver = {
"gem",
gem_pci_methods,
sizeof(struct gem_pci_softc)
};
DRIVER_MODULE(if_gem, pci, gem_pci_driver, gem_devclass, 0, 0);
struct gem_pci_dev {
u_int32_t gpd_devid;
char *gpd_desc;
} gem_pci_devlist[] = {
{ 0x1101108e, "Sun ERI 10/100 Ethernet Adaptor" },
{ 0x2bad108e, "Sun GEM Gigabit Ethernet Adaptor" },
{ 0x0021106b, "Apple GMAC Ethernet Adaptor" },
{ 0x0024106b, "Apple GMAC2 Ethernet Adaptor" },
{ 0, NULL }
};
/*
* Attach routines need to be split out to different bus-specific files.
*/
static int
gem_pci_probe(dev)
device_t dev;
{
int i;
u_int32_t devid;
devid = pci_get_devid(dev);
for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
if (devid == gem_pci_devlist[i].gpd_devid) {
device_set_desc(dev, gem_pci_devlist[i].gpd_desc);
return (0);
}
}
return (ENXIO);
}
static int
gem_pci_attach(dev)
device_t dev;
{
struct gem_pci_softc *gsc = device_get_softc(dev);
struct gem_softc *sc = &gsc->gsc_gem;
sc->sc_dev = dev;
sc->sc_pci = 1; /* XXX */
gsc->gsc_srid = PCI_GEM_BASEADDR;
gsc->gsc_sres = bus_alloc_resource(dev, SYS_RES_MEMORY, &gsc->gsc_srid,
0, ~0, 1, RF_ACTIVE);
if (gsc->gsc_sres == NULL) {
device_printf(dev, "failed to allocate bus space resource\n");
return (ENXIO);
}
gsc->gsc_irid = 0;
gsc->gsc_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &gsc->gsc_irid, 0,
~0, 1, RF_SHAREABLE | RF_ACTIVE);
if (gsc->gsc_ires == NULL) {
device_printf(dev, "failed to allocate interrupt resource\n");
goto fail_sres;
}
sc->sc_bustag = rman_get_bustag(gsc->gsc_sres);
sc->sc_h = rman_get_bushandle(gsc->gsc_sres);
/* All platform that this driver is used on must provide this. */
OF_getetheraddr(dev, sc->sc_arpcom.ac_enaddr);
/*
* call the main configure
*/
if (gem_attach(sc) != 0) {
device_printf(dev, "could not be configured\n");
goto fail_ires;
}
if (bus_setup_intr(dev, gsc->gsc_ires, INTR_TYPE_NET, gem_intr, sc,
&gsc->gsc_ih) != 0) {
device_printf(dev, "failed to set up interrupt\n");
goto fail_ires;
}
return (0);
fail_ires:
bus_release_resource(dev, SYS_RES_IRQ, gsc->gsc_irid, gsc->gsc_ires);
fail_sres:
bus_release_resource(dev, SYS_RES_MEMORY, gsc->gsc_srid, gsc->gsc_sres);
return (ENXIO);
}

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sys/dev/gem/if_gemreg.h Normal file
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/*
* Copyright (C) 2001 Eduardo Horvath.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: NetBSD: gemreg.h,v 1.2 2001/10/18 03:33:33 thorpej Exp
*
* $FreeBSD$
*/
#ifndef _IF_GEMREG_H
#define _IF_GEMREG_H
/* Register definitions for Sun GEM gigabit ethernet */
#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
#define GEM_CONFIG 0x0004 /* config reg */
#define GEM_STATUS 0x000c /* status reg */
/* Note: Reading the status reg clears bits 0-6 */
#define GEM_INTMASK 0x0010
#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
#define GEM_STATUS_ALIAS 0x001c
/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */
#define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */
#define GEM_ERROR_MASK 0x1004
#define GEM_BIF_CONFIG 0x1008 /* BIF config reg */
#define GEM_BIF_DIAG 0x100c
#define GEM_RESET 0x1010 /* Software reset register */
/* Bits in GEM_SEB register */
#define GEM_SEB_ARB 0x000000002 /* Arbitration status */
#define GEM_SEB_RXWON 0x000000004
/* Bits in GEM_CONFIG register */
#define GEM_CONFIG_BURST_64 0x000000000 /* 0->infininte, 1->64KB */
#define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infininte, 1->64KB */
#define GEM_CONFIG_TXDMA_LIMIT 0x00000003e
#define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0
#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1
#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6
/* Top part of GEM_STATUS has TX completion information */
#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */
/* Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. */
#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */
#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */
#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */
#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */
#define GEM_INTR_RX_NOBUF 0x000000020
#define GEM_INTR_RX_TAG_ERR 0x000000040
#define GEM_INTR_PCS 0x000002000
#define GEM_INTR_TX_MAC 0x000004000
#define GEM_INTR_RX_MAC 0x000008000
#define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */
#define GEM_INTR_MIF 0x000020000
#define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */
#define GEM_INTR_BITS "\177\020" \
"b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \
"b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \
"b\15PCS\0b\16TXMAC\0b\17RXMAC\0" \
"b\20MAC_CONTROL\0b\21MIF\0b\22BERR\0\0" \
/* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */
#define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */
#define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */
#define GEM_ERROR_STAT_OTHERS 0x000000004
/* GEM_BIF_CONFIG register bits */
#define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */
#define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */
#define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */
#define GEM_BIF_CONFIG_M66EN 0x000000008
/* GEM_RESET register bits -- TX and RX self clear when complete. */
#define GEM_RESET_TX 0x000000001 /* Reset TX half */
#define GEM_RESET_RX 0x000000002 /* Reset RX half */
#define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */
/* GEM TX DMA registers */
#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */
#define GEM_TX_CONFIG 0x2004
#define GEM_TX_RING_PTR_LO 0x2008
#define GEM_TX_RING_PTR_HI 0x200c
#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */
#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */
#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */
#define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */
#define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */
#define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */
#define GEM_TX_DATA_PTR_LO 0x2030
#define GEM_TX_DATA_PTR_HI 0x2034
#define GEM_TX_COMPLETION 0x2100
#define GEM_TX_FIFO_ADDRESS 0x2104
#define GEM_TX_FIFO_TAG 0x2108
#define GEM_TX_FIFO_DATA_LO 0x210c
#define GEM_TX_FIFO_DATA_HI_T1 0x2110
#define GEM_TX_FIFO_DATA_HI_T0 0x2114
#define GEM_TX_FIFO_SIZE 0x2118
#define GEM_TX_DEBUG 0x3028
/* GEM_TX_CONFIG register bits. */
#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */
#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */
#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */
#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */
#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */
#define GEM_RING_SZ_64 (1<<1)
#define GEM_RING_SZ_128 (2<<1)
#define GEM_RING_SZ_256 (3<<1)
#define GEM_RING_SZ_512 (4<<1)
#define GEM_RING_SZ_1024 (5<<1)
#define GEM_RING_SZ_2048 (6<<1)
#define GEM_RING_SZ_4096 (7<<1)
#define GEM_RING_SZ_8192 (8<<1)
/* GEM_TX_COMPLETION register bits */
#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */
/* GEM RX DMA registers */
#define GEM_RX_CONFIG 0x4000
#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */
#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */
#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */
#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */
#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */
#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */
#define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */
#define GEM_RX_PAUSE_THRESH 0x4020
#define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */
#define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */
#define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */
#define GEM_RX_COMPLETION 0x4104 /* First pending desc */
#define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */
#define GEM_RX_FIFO_ADDRESS 0x410c
#define GEM_RX_FIFO_TAG 0x4110
#define GEM_RX_FIFO_DATA_LO 0x4114
#define GEM_RX_FIFO_DATA_HI_T1 0x4118
#define GEM_RX_FIFO_DATA_HI_T0 0x411c
#define GEM_RX_FIFO_SIZE 0x4120
/* GEM_RX_CONFIG register bits. */
#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */
#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */
#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */
#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* checksum start offset */
#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */
#define GEM_THRSH_64 0
#define GEM_THRSH_128 1
#define GEM_THRSH_256 2
#define GEM_THRSH_512 3
#define GEM_THRSH_1024 4
#define GEM_THRSH_2048 5
#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24
#define GEM_RX_CONFIG_FBOFF_SHFT 10
#define GEM_RX_CONFIG_CXM_START_SHFT 13
/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
#define GEM_RX_PTH_XOFF_THRESH 0x000001ff
#define GEM_RX_PTH_XON_THRESH 0x07fc0000
/* GEM_RX_BLANKING register bits */
#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
#define GEM_RX_BLANKING_TIME 0x03fc0000 /* Delay intr for x ticks */
/* One tick is 1048 PCI clocs, or 16us at 66MHz */
/* GEM_MAC registers */
#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */
#define GEM_MAC_RXRESET 0x6004 /* ditto */
#define GEM_MAC_SEND_PAUSE_CMD 0x6008
#define GEM_MAC_TX_STATUS 0x6010
#define GEM_MAC_RX_STATUS 0x6014
#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */
#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */
#define GEM_MAC_RX_MASK 0x6024
#define GEM_MAC_CONTROL_MASK 0x6028
#define GEM_MAC_TX_CONFIG 0x6030
#define GEM_MAC_RX_CONFIG 0x6034
#define GEM_MAC_CONTROL_CONFIG 0x6038
#define GEM_MAC_XIF_CONFIG 0x603c
#define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */
#define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */
#define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */
#define GEM_MAC_SLOT_TIME 0x604c
#define GEM_MAC_MAC_MIN_FRAME 0x6050
#define GEM_MAC_MAC_MAX_FRAME 0x6054
#define GEM_MAC_PREAMBLE_LEN 0x6058
#define GEM_MAC_JAM_SIZE 0x605c
#define GEM_MAC_ATTEMPT_LIMIT 0x6060
#define GEM_MAC_CONTROL_TYPE 0x6064
#define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */
#define GEM_MAC_ADDR1 0x6084
#define GEM_MAC_ADDR2 0x6088
#define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */
#define GEM_MAC_ADDR4 0x6090
#define GEM_MAC_ADDR5 0x6094
#define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */
#define GEM_MAC_ADDR7 0x609c
#define GEM_MAC_ADDR8 0x60a0
#define GEM_MAC_ADDR_FILTER0 0x60a4
#define GEM_MAC_ADDR_FILTER1 0x60a8
#define GEM_MAC_ADDR_FILTER2 0x60ac
#define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */
#define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */
#define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */
#define GEM_MAC_HASH1 0x60c4
#define GEM_MAC_HASH2 0x60c8
#define GEM_MAC_HASH3 0x60cc
#define GEM_MAC_HASH4 0x60d0
#define GEM_MAC_HASH5 0x60d4
#define GEM_MAC_HASH6 0x60d8
#define GEM_MAC_HASH7 0x60dc
#define GEM_MAC_HASH8 0x60e0
#define GEM_MAC_HASH9 0x60e4
#define GEM_MAC_HASH10 0x60e8
#define GEM_MAC_HASH11 0x60ec
#define GEM_MAC_HASH12 0x60f0
#define GEM_MAC_HASH13 0x60f4
#define GEM_MAC_HASH14 0x60f8
#define GEM_MAC_HASH15 0x60fc
#define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */
#define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */
#define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */
#define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */
#define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */
#define GEM_MAC_PEAK_ATTEMPTS 0x6114
#define GEM_MAC_RX_FRAME_COUNT 0x6118
#define GEM_MAC_RX_LEN_ERR_CNT 0x611c
#define GEM_MAC_RX_ALIGN_ERR 0x6120
#define GEM_MAC_RX_CRC_ERR_CNT 0x6124
#define GEM_MAC_RX_CODE_VIOL 0x6128
#define GEM_MAC_RANDOM_SEED 0x6130
#define GEM_MAC_MAC_STATE 0x6134 /* MAC sstate machine reg */
/* GEM_MAC_SEND_PAUSE_CMD register bits */
#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff
#define GEM_MAC_PAUSE_CMD_SEND 0x00010000
/* GEM_MAC_TX_STATUS and _MASK register bits */
#define GEM_MAC_TX_XMIT_DONE 0x00000001
#define GEM_MAC_TX_UNDERRUN 0x00000002
#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004
#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */
#define GEM_MAC_TX_ECC_EXP 0x00000010
#define GEM_MAC_TX_LCC_EXP 0x00000020
#define GEM_MAC_TX_FCC_EXP 0x00000040
#define GEM_MAC_TX_DEFER_EXP 0x00000080
#define GEM_MAC_TX_PEAK_EXP 0x00000100
/* GEM_MAC_RX_STATUS and _MASK register bits */
#define GEM_MAC_RX_DONE 0x00000001
#define GEM_MAC_RX_OVERFLOW 0x00000002
#define GEM_MAC_RX_FRAME_CNT 0x00000004
#define GEM_MAC_RX_ALIGN_EXP 0x00000008
#define GEM_MAC_RX_CRC_EXP 0x00000010
#define GEM_MAC_RX_LEN_EXP 0x00000020
#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */
/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */
#define GEM_MAC_PAUSED 0x00000001 /* Pause received */
#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */
#define GEM_MAC_RESUME 0x00000004 /* exit pause state */
#define GEM_MAC_PAUSE_TIME 0xffff0000
/* GEM_MAC_XIF_CONFIG register bits */
#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */
#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */
#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */
#define GEM_MAC_XIF_MII_MODE 0x00000008 /* Select GMII/MII mode */
#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */
#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */
#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */
/* GEM_MAC_TX_CONFIG register bits */
#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */
#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */
#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collitions */
#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */
#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */
#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */
#define GEM_MAC_TX_NO_BACKOFF 0x00000040
#define GEM_MAC_TX_SLOWDOWN 0x00000080
#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */
#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */
/* Carrier Extension is required for half duplex Gbps operation */
/* GEM_MAC_RX_CONFIG register bits */
#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */
#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */
#define GEM_MAC_RX_STRIP_CRC 0x00000004
#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */
#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */
#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */
#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */
#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */
#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */
/*
* Carrier Extension enables reception of packet bursts generated by
* senders with carrier extension enabled.
*/
/* GEM_MAC_CONTROL_CONFIG bits */
#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */
#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */
#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */
/* GEM MIF registers */
/* Bit bang registers use low bit only */
#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */
#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */
#define GEM_MIF_BB_OUTPUT_ENAB 0x6208
#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */
#define GEM_MIF_CONFIG 0x6210
#define GEM_MIF_INTERRUPT_MASK 0x6214
#define GEM_MIF_BASIC_STATUS 0x6218
#define GEM_MIF_STATE_MACHINE 0x621c
/* GEM_MIF_FRAME bits */
#define GEM_MIF_FRAME_DATA 0x0000ffff
#define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */
#define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */
#define GEM_MIF_FRAME_REG_ADDR 0x007c0000
#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */
#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */
#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */
#define GEM_MIF_FRAME_READ 0x60020000
#define GEM_MIF_FRAME_WRITE 0x50020000
#define GEM_MIF_REG_SHIFT 18
#define GEM_MIF_PHY_SHIFT 23
/* GEM_MIF_CONFIG register bits */
#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select */
#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */
#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */
#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */
#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */
#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */
#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */
/* MDI0 is onboard tranciever MID1 is external, PHYAD for both is 0 */
/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */
#define GEM_MIF_STATUS 0x0000ffff
#define GEM_MIF_BASIC 0xffff0000
/*
* The Basic part is the last value read in the POLL field of the config
* register.
*
* The status part indicates the bits that have changed.
*/
/* The GEM PCS/Serial link register. */
#define GEM_MII_CONTROL 0x9000
#define GEM_MII_STATUS 0x9004
#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */
#define GEM_MII_ANLPAR 0x900c /* LP ability reg */
#define GEM_MII_CONFIG 0x9010
#define GEM_MII_STATE_MACHINE 0x9014
#define GEM_MII_INTERRUP_STATUS 0x9018
#define GEM_MII_DATAPATH_MODE 0x9050
#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */
#define GEM_MII_OUTPUT_SELECT 0x9058
#define GEM_MII_SLINK_STATUS 0x905c /* serial link status */
/* GEM_MII_CONTROL bits */
/*
* DO NOT TOUCH THIS REGISTER ON ERI -- IT HARD HANGS.
*/
#define GEM_MII_CONTROL_RESET 0x00008000
#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */
#define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */
#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */
#define GEM_MII_CONTROL_POWERDN 0x00000800
#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */
#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotioation */
#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */
#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */
/* GEM_MII_STATUS reg */
#define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */
#define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */
#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */
#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */
#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */
#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */
#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */
#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */
/* GEM_MII_ANAR and GEM_MII_ANLAR reg bits */
#define GEM_MII_ANEG_NP 0x00008000 /* next page bit */
#define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */
/* Link Partner Capability */
#define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */
#define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */
#define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */
#define GEM_MII_ANEG_HLF_DUPLX 0x00000040
#define GEM_MII_ANEG_FUL_DUPLX 0x00000020
/* GEM_MII_CONFIG reg */
#define GEM_MII_CONFIG_TIMER 0x0000001c /* link monitor timer values */
#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */
/* GEM_MII_DATAPATH_MODE reg */
#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */
#define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */
#define GEM_MII_DATAPATH_MII 0x00000004 /* Use MII, not PCS */
#define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */
/* GEM_MII_SLINK_CONTROL reg */
#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl */
#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */
#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */
#define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */
#define GEM_MII_SLINK_SELFTEST 0x000001c0
#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */
/* GEM_MII_SLINK_STATUS reg */
#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */
#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */
#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */
#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */
/* Wired GEM PHY addresses */
#define GEM_PHYAD_INTERNAL 1
#define GEM_PHYAD_EXTERNAL 0
/*
* GEM descriptor table structures.
*/
struct gem_desc {
uint64_t gd_flags;
uint64_t gd_addr;
};
/* Transmit flags */
#define GEM_TD_BUFSIZE 0x0000000000007fffLL
#define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */
#define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */
#define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */
#define GEM_TD_END_OF_PACKET 0x0000000040000000LL
#define GEM_TD_START_OF_PACKET 0x0000000080000000LL
#define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */
#define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */
/*
* Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF,
* GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group.
*/
/* Receive flags */
#define GEM_RD_CHECKSUM 0x000000000000ffffLL
#define GEM_RD_BUFSIZE 0x000000007fff0000LL
#define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */
#define GEM_RD_HASHVAL 0x0ffff00000000000LL
#define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */
#define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */
#define GEM_RD_BAD_CRC 0x4000000000000000LL
#define GEM_RD_BUFSHIFT 16
#define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT)
/* PCI support */
#define PCI_GEM_BASEADDR 0x10
#endif

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@ -0,0 +1,242 @@
/*
* Copyright (C) 2001 Eduardo Horvath.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: NetBSD: gemvar.h,v 1.5 2001/10/18 15:19:22 thorpej Exp
*
* $FreeBSD$
*/
#ifndef _IF_GEMVAR_H
#define _IF_GEMVAR_H
#include <sys/queue.h>
#include <sys/callout.h>
/*
* Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
*/
/*
* Transmit descriptor list size. This is arbitrary, but allocate
* enough descriptors for 64 pending transmissions and 16 segments
* per packet.
*/
#define GEM_NTXSEGS 16
#define GEM_TXQUEUELEN 64
#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
/*
* Receive descriptor list size. We have one Rx buffer per incoming
* packet, so this logic is a little simpler.
*/
#define GEM_NRXDESC 128
#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
/*
* Control structures are DMA'd to the GEM chip. We allocate them in
* a single clump that maps to a single DMA segment to make several things
* easier.
*/
struct gem_control_data {
/*
* The transmit descriptors.
*/
struct gem_desc gcd_txdescs[GEM_NTXDESC];
/*
* The receive descriptors.
*/
struct gem_desc gcd_rxdescs[GEM_NRXDESC];
};
#define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
/*
* Software state for transmit job mbufs (may be elements of mbuf chains).
*/
struct gem_txsoft {
struct mbuf *txs_mbuf; /* head of our mbuf chain */
bus_dmamap_t txs_dmamap; /* our DMA map */
int txs_firstdesc; /* first descriptor in packet */
int txs_lastdesc; /* last descriptor in packet */
int txs_ndescs; /* number of descriptors */
STAILQ_ENTRY(gem_txsoft) txs_q;
};
STAILQ_HEAD(gem_txsq, gem_txsoft);
/* Argument structure for busdma callback */
struct gem_txdma {
struct gem_softc *txd_sc;
int txd_nexttx;
int txd_lasttx;
int txd_nsegs;
int txd_flags;
#define GTXD_FIRST 1
#define GTXD_LAST 2
int txd_error;
};
/* Transmit job descriptor */
struct gem_txjob {
int txj_nexttx;
int txj_lasttx;
int txj_nsegs;
STAILQ_HEAD(, gem_txsoft) txj_txsq;
};
/*
* Software state for receive jobs.
*/
struct gem_rxsoft {
struct mbuf *rxs_mbuf; /* head of our mbuf chain */
bus_dmamap_t rxs_dmamap; /* our DMA map */
bus_addr_t rxs_paddr; /* physical address of the segment */
};
/*
* Software state per device.
*/
struct gem_softc {
struct arpcom sc_arpcom; /* arp common data */
device_t sc_miibus;
struct mii_data *sc_mii; /* MII media control */
device_t sc_dev; /* generic device information */
struct callout sc_tick_ch; /* tick callout */
/* The following bus handles are to be provided by the bus front-end */
bus_space_tag_t sc_bustag; /* bus tag */
bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
bus_dma_tag_t sc_dmatag; /* bus dma tag */
bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
bus_dmamap_t sc_dmamap; /* bus dma handle */
bus_space_handle_t sc_h; /* bus space handle for all regs */
int sc_phys[2]; /* MII instance -> PHY map */
int sc_mif_config; /* Selected MII reg setting */
int sc_pci; /* XXXXX -- PCI buses are LE. */
/*
* Ring buffer DMA stuff.
*/
bus_dma_segment_t sc_cdseg; /* control data memory */
int sc_cdnseg; /* number of segments */
bus_dmamap_t sc_cddmamap; /* control data DMA map */
bus_addr_t sc_cddma;
/*
* Software state for transmit and receive descriptors.
*/
struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
/*
* Control data structures.
*/
struct gem_control_data *sc_control_data;
#define sc_txdescs sc_control_data->gcd_txdescs
#define sc_rxdescs sc_control_data->gcd_rxdescs
int sc_txfree; /* number of free Tx descriptors */
int sc_txnext; /* next ready Tx descriptor */
struct gem_txsq sc_txfreeq; /* free Tx descsofts */
struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
int sc_rxptr; /* next ready RX descriptor/descsoft */
/* ========== */
int sc_inited;
int sc_debug;
int sc_flags;
/* Special hardware hooks */
void (*sc_hwreset) __P((struct gem_softc *));
void (*sc_hwinit) __P((struct gem_softc *));
};
#define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v))
#define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v))
#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
#define GEM_CDSPADDR(sc) ((sc)->sc_cddma + GEM_CDSPOFF)
#define GEM_CDTXSYNC(sc, x, n, ops) \
bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops)); \
#define GEM_CDRXSYNC(sc, x, ops) \
bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops))
#define GEM_CDSPSYNC(sc, ops) \
bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops))
#define GEM_INIT_RXDESC(sc, x) \
do { \
struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
struct mbuf *__m = __rxs->rxs_mbuf; \
\
__m->m_data = __m->m_ext.ext_buf; \
__rxd->gd_addr = \
GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
__rxd->gd_flags = \
GEM_DMA_WRITE((sc), \
(((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
} while (0)
#ifdef _KERNEL
extern devclass_t gem_devclass;
int gem_attach __P((struct gem_softc *));
int gem_detach __P((struct gem_softc *));
void gem_intr __P((void *));
int gem_mediachange __P((struct ifnet *));
void gem_mediastatus __P((struct ifnet *, struct ifmediareq *));
void gem_reset __P((struct gem_softc *));
/* MII methods & callbacks */
int gem_mii_readreg __P((device_t, int, int));
int gem_mii_writereg __P((device_t, int, int, int));
void gem_mii_statchg __P((device_t));
#endif /* _KERNEL */
#endif