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Close PR #8384:

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Revert the transmission packet queueing strategy changes. Clearly I missed
something while debugging this, although I never encountered any problems
on my test machines.

Also make one other minor change: jack up the TX reclaim threshold for
3c90xB adapters in order to stave off 'transmission error: 82' errors.

Document the existence of the tx reclaim register (for inspecting the
current reclaim threshold) in register window 5 (if_xlreg.h).
This commit is contained in:
Bill Paul 1998-10-22 15:52:25 +00:00
parent 43a2c34c47
commit 447c20659b
2 changed files with 39 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
sys/pci/if_xl.c
View File

@ -29,7 +29,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: if_xl.c,v 1.13 1998/10/09 03:59:23 wpaul Exp $
* $Id: if_xl.c,v 1.57 1998/10/22 15:35:06 wpaul Exp $
*/
/*
@ -147,7 +147,7 @@
#ifndef lint
static char rcsid[] =
"$Id: if_xl.c,v 1.13 1998/10/09 03:59:23 wpaul Exp $";
"$Id: if_xl.c,v 1.57 1998/10/22 15:35:06 wpaul Exp $";
#endif
/*
@ -1704,7 +1704,6 @@ static int xl_list_tx_init(sc)
cd->xl_tx_free = &cd->xl_tx_chain[0];
cd->xl_tx_tail = cd->xl_tx_head = NULL;
sc->xl_txeoc = 1;
return(0);
}
@ -1940,16 +1939,15 @@ static void xl_txeof(sc)
if (sc->xl_cdata.xl_tx_head == NULL) {
ifp->if_flags &= ~IFF_OACTIVE;
sc->xl_cdata.xl_tx_tail = NULL;
sc->xl_txeoc = 1;
if (sc->xl_want_auto)
xl_autoneg_mii(sc, XL_FLAG_SCHEDDELAY, 1);
} else {
sc->xl_txeoc = 0;
CSR_WRITE_4(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
xl_wait(sc);
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
!CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
vtophys(sc->xl_cdata.xl_tx_head->xl_ptr));
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
}
}
return;
@ -1981,6 +1979,10 @@ static void xl_txeoc(sc)
* first generation 3c90X chips.
*/
CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
if (sc->xl_type == XL_TYPE_905B) {
CSR_WRITE_2(sc, XL_COMMAND,
XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
}
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
} else {
@ -2271,21 +2273,21 @@ static void xl_start(ifp)
* Queue the packets. If the TX channel is clear, update
* the downlist pointer register.
*/
if (sc->xl_cdata.xl_tx_head == NULL) {
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
xl_wait(sc);
if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
vtophys(start_tx->xl_ptr);
sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
~XL_TXSTAT_DL_INTR;
} else {
sc->xl_cdata.xl_tx_head = start_tx;
sc->xl_cdata.xl_tx_tail = cur_tx;
if (sc->xl_txeoc) {
sc->xl_txeoc = 0;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
xl_wait(sc);
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
vtophys(start_tx->xl_ptr));
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
}
} else {
sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
sc->xl_cdata.xl_tx_tail = start_tx;
CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr));
}
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
XL_SEL_WIN(7);
@ -2380,6 +2382,20 @@ static void xl_init(xsc)
*/
CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
/*
* If this is a 3c905B, also set the tx reclaim threshold.
* This helps cut down on the number of tx reclaim errors
* that could happen on a busy network. The chip multiplies
* the register value by 16 to obtain the actual threshold
* in bytes, so we divide by 16 when setting the value here.
* The existing threshold value can be examined by reading
* the register at offset 9 in window 5.
*/
if (sc->xl_type == XL_TYPE_905B) {
CSR_WRITE_2(sc, XL_COMMAND,
XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
}
/* Set RX filter bits. */
XL_SEL_WIN(5);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);

4
sys/pci/if_xlreg.h
View File

@ -29,7 +29,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: if_xlreg.h,v 1.6 1998/10/09 03:59:24 wpaul Exp $
* $Id: if_xlreg.h,v 1.19 1998/10/22 15:35:06 wpaul Exp $
*/
#define XL_EE_READ 0x0080 /* read, 5 bit address */
@ -361,6 +361,7 @@
*/
#define XL_W5_STAT_ENB 0x0C
#define XL_W5_INTR_ENB 0x0A
#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */
#define XL_W5_RX_FILTER 0x08
#define XL_W5_RX_EARLYTHRESH 0x06
#define XL_W5_TX_AVAILTHRESH 0x02
@ -554,7 +555,6 @@ struct xl_softc {
u_int8_t xl_want_auto;
u_int8_t xl_autoneg;
u_int8_t xl_stats_no_timeout;
u_int8_t xl_txeoc;
caddr_t xl_ldata_ptr;
struct xl_list_data *xl_ldata;
struct xl_chain_data xl_cdata;