e1000: Re-arm link changes

A change to MSI-X link handler was somehow causing issues on
MSI-based em(4) NICs.

Revert the change based on user reports and testing.

PR:		258551
Reported by:	Franco Fichtner <franco@opnsense.org>, t_uemura@macome.co.jp
Reviewed by:	markj, Franco Fichtner <franco@opnsense.org>
Tested by:	t_uemura@macome.co.jp
MFC after:	1 day
This commit is contained in:
Kevin Bowling 2021-09-27 09:17:48 -07:00
parent 4e50efb194
commit 450c3f8b3d

View File

@ -1495,7 +1495,6 @@ em_msix_link(void *arg)
{
struct e1000_softc *sc = arg;
u32 reg_icr;
bool notlink = false;
++sc->link_irq;
MPASS(sc->hw.back != NULL);
@ -1506,17 +1505,14 @@ em_msix_link(void *arg)
if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
em_handle_link(sc->ctx);
else
notlink = true;
/* Re-arm for other/spurious interrupts */
if (notlink && sc->hw.mac.type >= igb_mac_min) {
/* Re-arm unconditionally */
if (sc->hw.mac.type >= igb_mac_min) {
E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
} else if (sc->hw.mac.type == e1000_82574) {
if (notlink)
E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC |
E1000_IMS_OTHER);
E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC |
E1000_IMS_OTHER);
/*
* Because we must read the ICR for this interrupt it may
* clear other causes using autoclear, for this reason we
@ -1524,7 +1520,8 @@ em_msix_link(void *arg)
*/
if (reg_icr)
E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims);
}
} else
E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
return (FILTER_HANDLED);
}
@ -1873,13 +1870,6 @@ em_if_update_admin_status(if_ctx_t ctx)
if (hw->mac.type < em_mac_min)
lem_smartspeed(sc);
else if (hw->mac.type >= igb_mac_min &&
sc->intr_type == IFLIB_INTR_MSIX) {
E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
} else if (hw->mac.type == e1000_82574 &&
sc->intr_type == IFLIB_INTR_MSIX)
E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
}
static void