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Import version 3.60.03.006 of the TWA driver:

Browse Source 
This patch does the following:

- Remove un-necessary code that is not even compiling into the driver
 under TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST defines.
- Remove bundled firmware image and associated "files" entry for tw_cl_fwimg.c
- Remove bundled firmware flashing routines. We now have tw_update userspace
 FreeBSD controller flash utility.
- Fix driver crash on load due to shared interrupt.
- Fix 2 lock leaks for Giant lock.
- Fix CCB leak.
- Add support for 9650SE controllers.

Many thanks to 3Ware/AMCC for continuing to support FreeBSD.
This commit is contained in:
Scott Long 2007-05-09 04:16:32 +00:00
parent c085f6bbf6
commit 4511a5c893
21 changed files with 105 additions and 48828 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sys/conf/files
View File

@ -1022,8 +1022,6 @@ dev/tdfx/tdfx_linux.c optional tdfx_linux tdfx compat_linux
dev/tdfx/tdfx_pci.c optional tdfx pci
dev/ti/if_ti.c optional ti pci
dev/trm/trm.c optional trm
dev/twa/tw_cl_fwimg.c optional twa \
compile-with "${NORMAL_C} -I$S/dev/twa"
dev/twa/tw_cl_init.c optional twa \
compile-with "${NORMAL_C} -I$S/dev/twa"
dev/twa/tw_cl_intr.c optional twa \

84
sys/dev/twa/tw_cl.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -50,11 +51,6 @@
#define TW_CLI_RESET_TIMEOUT_PERIOD 60 /* seconds */
#define TW_CLI_MAX_RESET_ATTEMPTS 2
#ifdef TW_OSL_FLASH_FIRMWARE
/* Number of chunks the fw image is broken into, while flashing. */
#define TW_CLI_NUM_FW_IMAGE_CHUNKS 500
#endif /* TW_OSL_FLASH_FIRMWARE */
/* Possible values of ctlr->state. */
/* Initialization done, and controller is active. */
#define TW_CLI_CTLR_STATE_ACTIVE (1<<0)
@ -144,19 +140,6 @@ struct tw_cli_ctlr_context {
OSL & CL. */
struct tw_cli_req_context *req_ctxt_buf;/* pointer to the array of CL's
internal request context pkts */
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
TW_UINT32 free_req_ids[TW_CL_MAX_SIMULTANEOUS_REQUESTS];
/* Array of free req_id's */
struct tw_cli_req_context *busy_reqs[TW_CL_MAX_SIMULTANEOUS_REQUESTS + 1];
/* Array of busy reqs -- index is req_id */
TW_UINT32 free_req_head;
TW_UINT32 free_req_tail;
TW_UINT32 num_free_req_ids;
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
struct tw_cl_command_packet *cmd_pkt_buf;/* ptr to array of cmd pkts */
TW_UINT64 cmd_pkt_phys; /* phys addr of cmd_pkt_buf */
@ -171,11 +154,6 @@ struct tw_cli_ctlr_context {
/* Request queues and arrays. */
struct tw_cl_link req_q_head[TW_CLI_Q_COUNT];
#ifdef TW_OSL_FLASH_FIRMWARE
TW_VOID *flash_dma_mem; /* mem for flashing fw image */
TW_UINT64 flash_dma_mem_phys;/* flash_dma_mem phys addr */
#endif /* TW_OSL_FLASH_FIRMWARE */
TW_UINT8 *internal_req_data;/* internal req data buf */
TW_UINT64 internal_req_data_phys;/* phys addr of internal
req data buf */
@ -294,13 +272,6 @@ tw_cli_req_q_insert_head(struct tw_cli_req_context *req, TW_UINT8 q_type)
{
struct tw_cli_ctlr_context *ctlr = req->ctlr;
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) ||
((q_type == TW_CLI_PENDING_Q) &&
(!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL))))
return;
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock);
TW_CL_Q_INSERT_HEAD(&(ctlr->req_q_head[q_type]), &(req->link));
TW_CLI_Q_INSERT(ctlr, q_type);
@ -315,45 +286,6 @@ tw_cli_req_q_insert_tail(struct tw_cli_req_context *req, TW_UINT8 q_type)
{
struct tw_cli_ctlr_context *ctlr = req->ctlr;
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) ||
((q_type == TW_CLI_PENDING_Q) &&
(!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL))))
return;
if ((q_type == TW_CLI_FREE_Q) &&
(!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL))) {
TW_SYNC_HANDLE sync_handle;
tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock);
if (req->state == TW_CLI_REQ_STATE_COMPLETE) {
if (ctlr->flags & TW_CL_DEFERRED_INTR_USED)
tw_osl_sync_io_block(ctlr->ctlr_handle,
&sync_handle);
} else {
if (!(ctlr->flags & TW_CL_DEFERRED_INTR_USED))
tw_osl_sync_isr_block(ctlr->ctlr_handle,
&sync_handle);
}
ctlr->free_req_ids[ctlr->free_req_tail] = req->request_id;
ctlr->busy_reqs[req->request_id] = TW_CL_NULL;
ctlr->free_req_tail = (ctlr->free_req_tail + 1) %
(ctlr->max_simult_reqs - 1);
ctlr->num_free_req_ids++;
if (req->state == TW_CLI_REQ_STATE_COMPLETE) {
if (ctlr->flags & TW_CL_DEFERRED_INTR_USED)
tw_osl_sync_io_unblock(ctlr->ctlr_handle,
&sync_handle);
} else {
if (!(ctlr->flags & TW_CL_DEFERRED_INTR_USED))
tw_osl_sync_isr_unblock(ctlr->ctlr_handle,
&sync_handle);
}
tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock);
return;
}
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock);
TW_CL_Q_INSERT_TAIL(&(ctlr->req_q_head[q_type]), &(req->link));
TW_CLI_Q_INSERT(ctlr, q_type);
@ -369,11 +301,6 @@ tw_cli_req_q_remove_head(struct tw_cli_ctlr_context *ctlr, TW_UINT8 q_type)
struct tw_cli_req_context *req = TW_CL_NULL;
struct tw_cl_link *link;
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q))
return(req);
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock);
if ((link = TW_CL_Q_FIRST_ITEM(&(ctlr->req_q_head[q_type]))) !=
TW_CL_NULL) {
@ -394,13 +321,6 @@ tw_cli_req_q_remove_item(struct tw_cli_req_context *req, TW_UINT8 q_type)
{
struct tw_cli_ctlr_context *ctlr = req->ctlr;
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) ||
((q_type == TW_CLI_PENDING_Q) &&
(!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL))))
return;
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock);
TW_CL_Q_REMOVE_ITEM(&(ctlr->req_q_head[q_type]), &(req->link));
TW_CLI_Q_REMOVE(ctlr, q_type);

18
sys/dev/twa/tw_cl_externs.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -50,18 +51,6 @@ extern TW_INT32 tw_cli_fw_img_size;
extern TW_INT8 *tw_cli_severity_string_table[];
#ifdef TW_OSL_FLASH_FIRMWARE
/* Functions in tw_cl_init.c */
/* Flash bundled firmware image onto controller. */
extern TW_INT32 tw_cli_flash_firmware(struct tw_cli_ctlr_context *ctlr);
/* Hard reset the controller. */
extern TW_INT32 tw_cli_hard_reset(struct tw_cli_ctlr_context *ctlr);
#endif /* TW_OSL_FLASH_FIRMWARE */
/* Do controller initialization. */
extern TW_INT32 tw_cli_start_ctlr(struct tw_cli_ctlr_context *ctlr);
@ -197,9 +186,6 @@ extern TW_INT32 tw_cli_poll_status(struct tw_cli_ctlr_context *ctlr,
/* Get a free CL internal request context packet. */
extern struct tw_cli_req_context *
tw_cli_get_request(struct tw_cli_ctlr_context *ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, struct tw_cl_req_packet *req_pkt
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
);
/* Notify OSL of controller info (fw/BIOS versions, etc.). */

6
sys/dev/twa/tw_cl_fwif.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -134,7 +135,6 @@
/* Misc defines. */
#define TWA_BUNDLED_FW_VERSION_STRING "3.02.00.004"
#define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001
#define TWA_64BIT_SG_ADDRESSES 0x00000001
#define TWA_EXTENDED_INIT_CONNECT 0x00000002
@ -152,8 +152,6 @@
#define TWA_ARCH_ID_9K_X 0x6 /* 9000 PCI-X controllers */
#define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001
#define TWA_CTLR_FW_COMPATIBLE 0x00000002
#define TWA_BUNDLED_FW_SAFE_TO_FLASH 0x00000004
#define TWA_CTLR_FW_RECOMMENDS_FLASH 0x00000008
#define TWA_SENSE_DATA_LENGTH 18

47792
sys/dev/twa/tw_cl_fwimg.c
View File

File diff suppressed because it is too large Load Diff

526
sys/dev/twa/tw_cl_init.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -63,7 +64,8 @@ tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id)
{
if ((vendor_id == TW_CL_VENDOR_ID) &&
((device_id == TW_CL_DEVICE_ID_9K) ||
(device_id == TW_CL_DEVICE_ID_9K_X)))
(device_id == TW_CL_DEVICE_ID_9K_X) ||
(device_id == TW_CL_DEVICE_ID_9K_E)))
return(TW_CL_TRUE);
return(TW_CL_FALSE);
}
@ -113,6 +115,7 @@ tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
break;
case TW_CL_DEVICE_ID_9K_X:
case TW_CL_DEVICE_ID_9K_E:
switch(bar_type) {
case TW_CL_BAR_TYPE_IO:
*bar_num = 2;
@ -162,8 +165,6 @@ tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
* non_dma_mem_size -- # of bytes of memory needed for
* non-DMA purposes
* dma_mem_size -- # of bytes of DMA'able memory needed
* flash_dma_mem_size -- # of bytes of DMA'able memory
* needed for firmware flash, if applicable
* per_req_dma_mem_size -- # of bytes of DMA'able memory
* needed per request, if applicable
* per_req_non_dma_mem_size -- # of bytes of memory needed
@ -178,15 +179,6 @@ tw_cl_get_mem_requirements(struct tw_cl_ctlr_handle *ctlr_handle,
TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
TW_INT32 max_aens, TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
#ifdef TW_OSL_FLASH_FIRMWARE
, TW_UINT32 *flash_dma_mem_size
#endif /* TW_OSL_FLASH_FIRMWARE */
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
, TW_UINT32 *per_req_dma_mem_size
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_UINT32 *per_req_non_dma_mem_size
#endif /* TW_OSL_N0N_DMA_MEM_ALLOC_PER_REQUEST */
)
{
if (device_id == 0)
@ -211,20 +203,11 @@ tw_cl_get_mem_requirements(struct tw_cl_ctlr_handle *ctlr_handle,
* the controller context, request packets (including the 1 needed for
* CL internal requests), and event packets.
*/
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
*non_dma_mem_size = sizeof(struct tw_cli_ctlr_context) +
(sizeof(struct tw_cli_req_context)) +
(sizeof(struct tw_cl_event_packet) * max_aens);
*per_req_non_dma_mem_size = sizeof(struct tw_cli_req_context);
#else /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
*non_dma_mem_size = sizeof(struct tw_cli_ctlr_context) +
(sizeof(struct tw_cli_req_context) * (max_simult_reqs + 1)) +
(sizeof(struct tw_cl_event_packet) * max_aens);
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
/*
* Total DMA'able memory needed is the sum total of memory needed for
@ -232,31 +215,10 @@ tw_cl_get_mem_requirements(struct tw_cl_ctlr_handle *ctlr_handle,
* requests), and memory needed to hold the payload for internal
* requests.
*/
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
*dma_mem_size = sizeof(struct tw_cl_command_packet) +
TW_CLI_SECTOR_SIZE;
*per_req_dma_mem_size = sizeof(struct tw_cl_command_packet);
#else /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
*dma_mem_size = (sizeof(struct tw_cl_command_packet) *
(max_simult_reqs + 1)) + (TW_CLI_SECTOR_SIZE);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
#ifdef TW_OSL_FLASH_FIRMWARE
/* Memory needed to hold the firmware image while flashing. */
*flash_dma_mem_size =
((tw_cli_fw_img_size / TW_CLI_NUM_FW_IMAGE_CHUNKS) +
511) & ~511;
/* (TWA_SG_ELEMENT_SIZE_FACTOR(device_id) - 1)) &
~(TWA_SG_ELEMENT_SIZE_FACTOR(device_id) - 1); */
#endif /* TW_OSL_FLASH_FIRMWARE */
return(0);
}
@ -276,9 +238,6 @@ tw_cl_get_mem_requirements(struct tw_cl_ctlr_handle *ctlr_handle,
* non_dma_mem -- ptr to allocated non-DMA memory
* dma_mem -- ptr to allocated DMA'able memory
* dma_mem_phys -- physical address of dma_mem
* flash_dma_mem -- ptr to allocated DMA'able memory
* needed for firmware flash, if applicable
* flash_dma_mem_phys -- physical address of flash_dma_mem
* Output: None
* Return value: 0 -- success
* non-zero-- failure
@ -287,10 +246,6 @@ TW_INT32
tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
TW_VOID *non_dma_mem, TW_VOID *dma_mem, TW_UINT64 dma_mem_phys
#ifdef TW_OSL_FLASH_FIRMWARE
, TW_VOID *flash_dma_mem,
TW_UINT64 flash_dma_mem_phys
#endif /* TW_OSL_FLASH_FIRMWARE */
)
{
struct tw_cli_ctlr_context *ctlr;
@ -319,10 +274,6 @@ tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
}
if ((non_dma_mem == TW_CL_NULL) || (dma_mem == TW_CL_NULL)
#ifdef TW_OSL_FLASH_FIRMWARE
|| ((flags & TW_CL_FLASH_FIRMWARE) ?
(flash_dma_mem == TW_CL_NULL) : TW_CL_FALSE)
#endif /* TW_OSL_FLASH_FIRMWARE */
) {
tw_cl_create_event(ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
@ -332,27 +283,14 @@ tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
return(TW_OSL_ENOMEM);
}
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
tw_osl_memzero(non_dma_mem, sizeof(struct tw_cli_ctlr_context) +
sizeof(struct tw_cli_req_context) +
(sizeof(struct tw_cl_event_packet) * max_aens));
#else /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
tw_osl_memzero(non_dma_mem, sizeof(struct tw_cli_ctlr_context) +
(sizeof(struct tw_cli_req_context) * (max_simult_reqs + 1)) +
(sizeof(struct tw_cl_event_packet) * max_aens));
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
tw_osl_memzero(dma_mem,
sizeof(struct tw_cl_command_packet) +
TW_CLI_SECTOR_SIZE);
#else /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
tw_osl_memzero(dma_mem,
(sizeof(struct tw_cl_command_packet) *
(max_simult_reqs + 1)) +
TW_CLI_SECTOR_SIZE);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
free_non_dma_mem = (TW_UINT8 *)non_dma_mem;
@ -369,11 +307,6 @@ tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
ctlr->max_simult_reqs = max_simult_reqs + 1;
ctlr->max_aens_supported = max_aens;
#ifdef TW_OSL_FLASH_FIRMWARE
ctlr->flash_dma_mem = flash_dma_mem;
ctlr->flash_dma_mem_phys = flash_dma_mem_phys;
#endif /* TW_OSL_FLASH_FIRMWARE */
/* Initialize queues of CL internal request context packets. */
tw_cli_req_q_init(ctlr, TW_CLI_FREE_Q);
tw_cli_req_q_init(ctlr, TW_CLI_BUSY_Q);
@ -397,7 +330,9 @@ tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
* with command register writes.
*/
if ((ctlr->flags & TW_CL_64BIT_ADDRESSES) &&
(ctlr->device_id == TW_CL_DEVICE_ID_9K)) {
((ctlr->device_id == TW_CL_DEVICE_ID_9K) ||
(ctlr->device_id == TW_CL_DEVICE_ID_9K_X) ||
(ctlr->device_id == TW_CL_DEVICE_ID_9K_E))) {
ctlr->state |= TW_CLI_CTLR_STATE_G66_WORKAROUND_NEEDED;
ctlr->intr_lock = ctlr->io_lock;
} else {
@ -410,9 +345,7 @@ tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
ctlr->req_ctxt_buf = (struct tw_cli_req_context *)free_non_dma_mem;
free_non_dma_mem += (sizeof(struct tw_cli_req_context) *
(
#ifndef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
max_simult_reqs +
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
1));
ctlr->cmd_pkt_buf = (struct tw_cl_command_packet *)dma_mem;
@ -421,59 +354,31 @@ tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
ctlr->internal_req_data = (TW_UINT8 *)
(ctlr->cmd_pkt_buf +
(
#ifndef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
max_simult_reqs +
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
1));
ctlr->internal_req_data_phys = ctlr->cmd_pkt_phys +
(sizeof(struct tw_cl_command_packet) *
(
#ifndef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
max_simult_reqs +
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
1));
for (i = 0;
i < (
#ifndef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
max_simult_reqs +
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
1); i++) {
req = &(ctlr->req_ctxt_buf[i]);
#ifndef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = &(ctlr->cmd_pkt_buf[i]);
req->cmd_pkt_phys = ctlr->cmd_pkt_phys +
(i * sizeof(struct tw_cl_command_packet));
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->request_id = i;
req->ctlr = ctlr;
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
/* Insert request into the free queue. */
tw_cli_req_q_insert_tail(req, TW_CLI_FREE_Q);
}
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
ctlr->free_req_head = i - 1;
ctlr->free_req_tail = i - 1;
for (; i < (max_simult_reqs + 1); i++)
ctlr->free_req_ids[i - 1] = i;
ctlr->num_free_req_ids = max_simult_reqs;
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
/* Initialize the AEN queue. */
ctlr->aen_queue = (struct tw_cl_event_packet *)free_non_dma_mem;
@ -517,317 +422,12 @@ tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
return(error);
}
#ifdef TW_OSL_FLASH_FIRMWARE
/*
* Function name: tw_cli_flash_firmware
* Description: Flashes bundled firmware image onto controller.
*
* Input: ctlr -- ptr to per ctlr structure
* Output: None
* Return value: 0 -- success
* non-zero-- failure
*/
TW_INT32
tw_cli_flash_firmware(struct tw_cli_ctlr_context *ctlr)
{
struct tw_cli_req_context *req;
struct tw_cl_command_header *cmd_hdr;
struct tw_cl_command_download_firmware *cmd;
TW_UINT32 fw_img_chunk_size;
TW_UINT32 num_chunks;
TW_UINT32 this_chunk_size = 0;
TW_INT32 remaining_img_size = 0;
TW_INT32 hard_reset_needed = TW_CL_FALSE;
TW_INT32 error = TW_OSL_EGENFAILURE;
TW_UINT32 i;
tw_cli_dbg_printf(3, ctlr->ctlr_handle, tw_osl_cur_func(), "entered");
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_CL_NULL
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL) {
/* No free request packets available. Can't proceed. */
error = TW_OSL_EBUSY;
goto out;
}
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = ctlr->cmd_pkt_buf;
req->cmd_pkt_phys = ctlr->cmd_pkt_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
/*
* Determine amount of memory needed to hold a chunk of the
* firmware image. As yet, the Download_Firmware command does not
* support SG elements that are ctlr->sg_size_factor multiples. It
* requires them to be 512-byte multiples.
*/
fw_img_chunk_size = ((tw_cli_fw_img_size / TW_CLI_NUM_FW_IMAGE_CHUNKS) +
511) & ~511;
/* (ctlr->sg_size_factor - 1)) &
~(ctlr->sg_size_factor - 1); */
/* Calculate the actual number of chunks needed. */
num_chunks = (tw_cli_fw_img_size / fw_img_chunk_size) +
((tw_cli_fw_img_size % fw_img_chunk_size) ? 1 : 0);
req->data = ctlr->flash_dma_mem;
req->data_phys = ctlr->flash_dma_mem_phys;
remaining_img_size = tw_cli_fw_img_size;
cmd_hdr = &(req->cmd_pkt->cmd_hdr);
cmd = &(req->cmd_pkt->command.cmd_pkt_7k.download_fw);
for (i = 0; i < num_chunks; i++) {
/* Build a cmd pkt for downloading firmware. */
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_packet));
cmd_hdr->header_desc.size_header = 128;
/* sgl_offset (offset in dwords, to sg list) is 2. */
cmd->sgl_off__opcode =
BUILD_SGL_OFF__OPCODE(2, TWA_FW_CMD_DOWNLOAD_FIRMWARE);
cmd->request_id = (TW_UINT8)(TW_CL_SWAP16(req->request_id));
cmd->unit = 0;
cmd->status = 0;
cmd->flags = 0;
cmd->param = TW_CL_SWAP16(8); /* prom image */
if (i != (num_chunks - 1))
this_chunk_size = fw_img_chunk_size;
else /* last chunk */
this_chunk_size = remaining_img_size;
remaining_img_size -= this_chunk_size;
tw_osl_memcpy(req->data, tw_cli_fw_img + (i * fw_img_chunk_size),
this_chunk_size);
/*
* The next line will effect only the last chunk.
*/
req->length = (this_chunk_size + 511) & ~511;
/* (ctlr->sg_size_factor - 1)) &
~(ctlr->sg_size_factor - 1); */
if (ctlr->flags & TW_CL_64BIT_ADDRESSES) {
((struct tw_cl_sg_desc64 *)(cmd->sgl))[0].address =
TW_CL_SWAP64(req->data_phys);
((struct tw_cl_sg_desc64 *)(cmd->sgl))[0].length =
TW_CL_SWAP32(req->length);
cmd->size = 2 + 3;
} else {
((struct tw_cl_sg_desc32 *)(cmd->sgl))[0].address =
TW_CL_SWAP32(req->data_phys);
((struct tw_cl_sg_desc32 *)(cmd->sgl))[0].length =
TW_CL_SWAP32(req->length);
cmd->size = 2 + 2;
}
error = tw_cli_submit_and_poll_request(req,
TW_CLI_REQUEST_TIMEOUT_PERIOD);
if (error) {
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x1005, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Firmware flash request could not be posted",
"error = %d\n", error);
if (error == TW_OSL_ETIMEDOUT)
/* clean-up done by tw_cli_submit_and_poll_request */
return(error);
break;
}
error = cmd->status;
if (((i == (num_chunks - 1)) && (error)) ||
((i != (num_chunks - 1)) &&
((error = cmd_hdr->status_block.error) !=
TWA_ERROR_MORE_DATA))) {
/*
* It's either that download of the last chunk
* failed, or the download of one of the earlier
* chunks failed with an error other than
* TWA_ERROR_MORE_DATA. Report the error.
*/
tw_cli_create_ctlr_event(ctlr,
TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR,
cmd_hdr);
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x1006, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Firmware flash failed",
"cmd = 0x%x, chunk # %d, cmd status = %d",
GET_OPCODE(cmd->sgl_off__opcode),
i, cmd->status);
/*
* Make a note to hard reset the controller,
* so that it doesn't wait for the remaining
* chunks. Don't call the hard reset function
* right here, since we have committed to having
* only 1 active internal request at a time, and
* this request has not yet been freed.
*/
hard_reset_needed = TW_CL_TRUE;
break;
}
} /* for */
out:
if (req)
tw_cli_req_q_insert_tail(req, TW_CLI_FREE_Q);
if (hard_reset_needed)
tw_cli_hard_reset(ctlr);
return(error);
}
/*
* Function name: tw_cli_hard_reset
* Description: Hard resets the controller.
*
* Input: ctlr -- ptr to per ctlr structure
* Output: None
* Return value: 0 -- success
* non-zero-- failure
*/
TW_INT32
tw_cli_hard_reset(struct tw_cli_ctlr_context *ctlr)
{
struct tw_cli_req_context *req;
struct tw_cl_command_reset_firmware *cmd;
TW_INT32 error;
tw_cli_dbg_printf(3, ctlr->ctlr_handle, tw_osl_cur_func(), "entered");
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_CL_NULL
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL)
return(TW_OSL_EBUSY);
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = ctlr->cmd_pkt_buf;
req->cmd_pkt_phys = ctlr->cmd_pkt_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
/* Build a cmd pkt for sending down the hard reset command. */
req->cmd_pkt->cmd_hdr.header_desc.size_header = 128;
cmd = &(req->cmd_pkt->command.cmd_pkt_7k.reset_fw);
cmd->res1__opcode =
BUILD_RES__OPCODE(0, TWA_FW_CMD_HARD_RESET_FIRMWARE);
cmd->size = 2;
cmd->request_id = (TW_UINT8)(TW_CL_SWAP16(req->request_id));
cmd->unit = 0;
cmd->status = 0;
cmd->flags = 0;
cmd->param = 0; /* don't reload FPGA logic */
req->data = TW_CL_NULL;
req->length = 0;
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x1017, 0x3, TW_CL_SEVERITY_INFO_STRING,
"Issuing hard (commanded) reset to the controller...",
" ");
error = tw_cli_submit_and_poll_request(req,
TW_CLI_REQUEST_TIMEOUT_PERIOD);
if (error) {
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x1007, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Hard reset request could not be posted",
"error = %d", error);
if (error == TW_OSL_ETIMEDOUT)
/* clean-up done by tw_cli_submit_and_poll_request */
return(error);
goto out;
}
if ((error = cmd->status)) {
tw_cli_create_ctlr_event(ctlr,
TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR,
&(req->cmd_pkt->cmd_hdr));
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x1008, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Hard reset request failed",
"error = %d", error);
}
if (ctlr->device_id == TW_CL_DEVICE_ID_9K_X) {
/*
* There's a hardware bug in the G133 ASIC, which can lead to
* PCI parity errors and hangs, if the host accesses any
* registers when the firmware is resetting the hardware, as
* part of a hard/soft reset. The window of time when the
* problem can occur is about 10 ms. Here, we will handshake
* with the firmware to find out when the firmware is pulling
* down the hardware reset pin, and wait for about 500 ms to
* make sure we don't access any hardware registers (for
* polling) during that window.
*/
ctlr->state |= TW_CLI_CTLR_STATE_RESET_PHASE1_IN_PROGRESS;
while (tw_cli_find_response(ctlr,
TWA_RESET_PHASE1_NOTIFICATION_RESPONSE) != TW_OSL_ESUCCESS)
tw_osl_delay(10);
tw_osl_delay(TWA_RESET_PHASE1_WAIT_TIME_MS * 1000);
ctlr->state &= ~TW_CLI_CTLR_STATE_RESET_PHASE1_IN_PROGRESS;
}
/* Wait for the MC_RDY bit to get set. */
if ((error = tw_cli_poll_status(ctlr, TWA_STATUS_MICROCONTROLLER_READY,
TW_CLI_RESET_TIMEOUT_PERIOD))) {
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT,
0x1018, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Micro-ctlr not ready following hard reset",
"error = %d", error);
}
out:
if (req)
tw_cli_req_q_insert_tail(req, TW_CLI_FREE_Q);
return(error);
}
#endif /* TW_OSL_FLASH_FIRMWARE */
/*
* Function name: tw_cli_start_ctlr
* Description: Establishes a logical connection with the controller.
* If bundled with firmware, determines whether or not
* to flash firmware, based on arch_id, fw SRL (Spec.
* Revision Level), branch & build #'s. Also determines
* whether or not the driver is compatible with the
* firmware on the controller, before proceeding to work
* with it.
* Determines whether or not the driver is compatible
* with the firmware on the controller, before proceeding
* to work with it.
*
* Input: ctlr -- ptr to per ctlr structure
* Output: None
@ -843,10 +443,6 @@ tw_cli_start_ctlr(struct tw_cli_ctlr_context *ctlr)
TW_UINT16 fw_on_ctlr_build = 0;
TW_UINT32 init_connect_result = 0;
TW_INT32 error = TW_OSL_ESUCCESS;
#ifdef TW_OSL_FLASH_FIRMWARE
TW_INT8 fw_flashed = TW_CL_FALSE;
TW_INT8 fw_flash_failed = TW_CL_FALSE;
#endif /* TW_OSL_FLASH_FIRMWARE */
tw_cli_dbg_printf(3, ctlr->ctlr_handle, tw_osl_cur_func(), "entered");
@ -887,67 +483,9 @@ tw_cli_start_ctlr(struct tw_cli_ctlr_context *ctlr)
"error = %d", error);
return(error);
}
#ifdef TW_OSL_FLASH_FIRMWARE
if ((ctlr->flags & TW_CL_FLASH_FIRMWARE) &&
(init_connect_result & TWA_BUNDLED_FW_SAFE_TO_FLASH) &&
(init_connect_result & TWA_CTLR_FW_RECOMMENDS_FLASH)) {
/*
* The bundled firmware is safe to flash, and the firmware
* on the controller recommends a flash. So, flash!
*/
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x100C, 0x3, TW_CL_SEVERITY_INFO_STRING,
"Flashing bundled firmware...",
" ");
if ((error = tw_cli_flash_firmware(ctlr))) {
fw_flash_failed = TW_CL_TRUE;
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x100D, 0x2, TW_CL_SEVERITY_WARNING_STRING,
"Unable to flash bundled firmware. "
"Attempting to work with fw on ctlr...",
" ");
} else {
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x100E, 0x3, TW_CL_SEVERITY_INFO_STRING,
"Successfully flashed bundled firmware",
" ");
fw_flashed = TW_CL_TRUE;
}
}
if (fw_flashed) {
/* The firmware was flashed. Have the new image loaded */
error = tw_cli_hard_reset(ctlr);
if (error)
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x100F, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Could not reset controller after flash!",
" ");
else /* Go through initialization again. */
error = tw_cli_start_ctlr(ctlr);
/*
* If hard reset of controller failed, we need to return.
* Otherwise, the above recursive call to tw_cli_start_ctlr
* will have completed the rest of the initialization (starting
* from tw_cli_drain_aen_queue below). Don't do it again.
* Just return.
*/
return(error);
} else
#endif /* TW_OSL_FLASH_FIRMWARE */
{
/*
* Either we are not bundled with a firmware image, or
* the bundled firmware is not safe to flash,
* or flash failed for some reason. See if we can at
* least work with the firmware on the controller in the
* current mode.
/* See if we can at least work with the firmware on the
* controller in the current mode.
*/
if (init_connect_result & TWA_CTLR_FW_COMPATIBLE) {
/* Yes, we can. Make note of the operating mode. */
@ -965,8 +503,7 @@ tw_cli_start_ctlr(struct tw_cli_ctlr_context *ctlr)
} else {
/*
* No, we can't. See if we can at least work with
* it in the base mode. We should never come here
* if firmware has just been flashed.
* it in the base mode.
*/
tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
@ -999,28 +536,6 @@ tw_cli_start_ctlr(struct tw_cli_ctlr_context *ctlr)
* compatible with our base mode. We cannot
* work with it. Bail...
*/
#ifdef TW_OSL_FLASH_FIRMWARE
if (fw_flash_failed)
tw_cl_create_event(ctlr->ctlr_handle,
TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x1012, 0x1,
TW_CL_SEVERITY_ERROR_STRING,
"Incompatible firmware on controller"
"...and could not flash bundled "
"firmware",
" ");
else
tw_cl_create_event(ctlr->ctlr_handle,
TW_CL_FALSE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
0x1013, 0x1,
TW_CL_SEVERITY_ERROR_STRING,
"Incompatible firmware on controller"
"...and bundled firmware not safe to "
"flash",
" ");
#endif /* TW_OSL_FLASH_FIRMWARE */
return(1);
}
/*
@ -1156,22 +671,9 @@ tw_cli_init_connection(struct tw_cli_ctlr_context *ctlr,
/* Get a request packet. */
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_CL_NULL
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL)
goto out;
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = ctlr->cmd_pkt_buf;
req->cmd_pkt_phys = ctlr->cmd_pkt_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
/* Build the cmd pkt. */

27
sys/dev/twa/tw_cl_intr.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -69,6 +70,10 @@ tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle)
tw_cli_dbg_printf(10, ctlr_handle, tw_osl_cur_func(), "entered");
/* If we don't have controller context, bail */
if (ctlr == NULL)
goto out;
/*
* Synchronize access between writes to command and control registers
* in 64-bit environments, on G66.
@ -79,7 +84,7 @@ tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle)
/* Read the status register to determine the type of interrupt. */
status_reg = TW_CLI_READ_STATUS_REGISTER(ctlr_handle);
if (tw_cli_check_ctlr_state(ctlr, status_reg))
goto out;
goto out_unlock;
/* Clear the interrupt. */
if (status_reg & TWA_STATUS_HOST_INTERRUPT) {
@ -114,10 +119,10 @@ tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle)
ctlr->resp_intr_pending = 1;
rc |= TW_CL_TRUE; /* request for a deferred isr call */
}
out:
out_unlock:
if (ctlr->state & TW_CLI_CTLR_STATE_G66_WORKAROUND_NEEDED)
tw_osl_free_lock(ctlr_handle, ctlr->io_lock);
out:
return(rc);
}
@ -290,11 +295,6 @@ tw_cli_process_resp_intr(struct tw_cli_ctlr_context *ctlr)
/* Response queue is not empty. */
resp = TW_CLI_READ_RESPONSE_QUEUE(ctlr->ctlr_handle);
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if (GET_RESP_ID(resp) >= 1)
req = ctlr->busy_reqs[GET_RESP_ID(resp)];
else
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
{
req = &(ctlr->req_ctxt_buf[GET_RESP_ID(resp)]);
}
@ -322,13 +322,6 @@ tw_cli_process_resp_intr(struct tw_cli_ctlr_context *ctlr)
req->state = TW_CLI_REQ_STATE_COMPLETE;
tw_cli_req_q_insert_tail(req, TW_CLI_COMPLETE_Q);
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
tw_osl_free_lock(ctlr->ctlr_handle, ctlr->intr_lock);
/* Call the CL internal callback, if there's one. */
if (req->tw_cli_callback)
req->tw_cli_callback(req);
tw_osl_get_lock(ctlr->ctlr_handle, ctlr->intr_lock);
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
}
/* Unmask the response interrupt. */
@ -337,10 +330,8 @@ tw_cli_process_resp_intr(struct tw_cli_ctlr_context *ctlr)
tw_osl_free_lock(ctlr->ctlr_handle, ctlr->intr_lock);
#ifndef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
/* Complete this, and other requests in the complete queue. */
tw_cli_process_complete_queue(ctlr);
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
return(error);
}

136
sys/dev/twa/tw_cl_io.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -96,9 +97,6 @@ tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle,
}
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, req_pkt
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL) {
tw_cli_dbg_printf(2, ctlr_handle, tw_osl_cur_func(),
"Out of request context packets: returning busy");
@ -107,17 +105,6 @@ tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle,
}
req_handle->cl_req_ctxt = req;
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = req_pkt->dma_mem;
req->cmd_pkt_phys = req_pkt->dma_mem_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->req_handle = req_handle;
req->orig_req = req_pkt;
req->tw_cli_callback = tw_cli_complete_io;
@ -184,23 +171,17 @@ tw_cli_submit_cmd(struct tw_cli_req_context *req)
TW_UINT32 status_reg;
TW_INT32 error;
TW_UINT8 notify_osl_of_ctlr_busy = TW_CL_FALSE;
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
TW_SYNC_HANDLE sync_handle;
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
tw_cli_dbg_printf(10, ctlr_handle, tw_osl_cur_func(), "entered");
/* Serialize access to the controller cmd queue. */
tw_osl_get_lock(ctlr_handle, ctlr->io_lock);
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if (req->flags & TW_CLI_REQ_FLAGS_EXTERNAL) {
if (!(ctlr->flags & TW_CL_DEFERRED_INTR_USED))
tw_osl_sync_isr_block(ctlr_handle, &sync_handle);
} else {
if (ctlr->flags & TW_CL_DEFERRED_INTR_USED)
tw_osl_sync_io_block(ctlr_handle, &sync_handle);
}
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
/* For 9650SE first write low 4 bytes */
if (ctlr->device_id == TW_CL_DEVICE_ID_9K_E)
tw_osl_write_reg(ctlr_handle,
TWA_COMMAND_QUEUE_OFFSET_LOW,
(TW_UINT32)(req->cmd_pkt_phys + sizeof(struct tw_cl_command_header)), 4);
/* Check to see if we can post a command. */
status_reg = TW_CLI_READ_STATUS_REGISTER(ctlr_handle);
@ -215,10 +196,8 @@ tw_cli_submit_cmd(struct tw_cli_req_context *req)
"Cmd queue full");
if ((req->flags & TW_CLI_REQ_FLAGS_INTERNAL)
#ifndef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
|| ((req_pkt) &&
(req_pkt->flags & TW_CL_REQ_RETRY_ON_BUSY))
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
) {
if (req->state != TW_CLI_REQ_STATE_PENDING) {
tw_cli_dbg_printf(2, ctlr_handle,
@ -237,28 +216,31 @@ tw_cli_submit_cmd(struct tw_cli_req_context *req)
tw_cli_dbg_printf(10, ctlr_handle, tw_osl_cur_func(),
"Submitting command");
/*
* The controller cmd queue is not full. Mark the request as
* currently being processed by the firmware, and move it into
* the busy queue. Then submit the cmd.
*/
/* Insert command into busy queue */
req->state = TW_CLI_REQ_STATE_BUSY;
tw_cli_req_q_insert_tail(req, TW_CLI_BUSY_Q);
TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle,
req->cmd_pkt_phys +
sizeof(struct tw_cl_command_header));
}
out:
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if (req->flags & TW_CLI_REQ_FLAGS_EXTERNAL) {
if (!(ctlr->flags & TW_CL_DEFERRED_INTR_USED))
tw_osl_sync_isr_unblock(ctlr_handle, &sync_handle);
} else {
if (ctlr->flags & TW_CL_DEFERRED_INTR_USED)
tw_osl_sync_io_unblock(ctlr_handle, &sync_handle);
if (ctlr->device_id == TW_CL_DEVICE_ID_9K_E) {
/* Now write the high 4 bytes */
tw_osl_write_reg(ctlr_handle,
TWA_COMMAND_QUEUE_OFFSET_HIGH,
(TW_UINT32)(((TW_UINT64)(req->cmd_pkt_phys + sizeof(struct tw_cl_command_header)))>>32), 4);
} else {
if (ctlr->flags & TW_CL_64BIT_ADDRESSES) {
/* First write the low 4 bytes, then the high 4. */
tw_osl_write_reg(ctlr_handle,
TWA_COMMAND_QUEUE_OFFSET_LOW,
(TW_UINT32)(req->cmd_pkt_phys + sizeof(struct tw_cl_command_header)), 4);
tw_osl_write_reg(ctlr_handle,
TWA_COMMAND_QUEUE_OFFSET_HIGH,
(TW_UINT32)(((TW_UINT64)(req->cmd_pkt_phys + sizeof(struct tw_cl_command_header)))>>32), 4);
} else
tw_osl_write_reg(ctlr_handle,
TWA_COMMAND_QUEUE_OFFSET,
(TW_UINT32)(req->cmd_pkt_phys + sizeof(struct tw_cl_command_header)), 4);
}
}
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
out:
tw_osl_free_lock(ctlr_handle, ctlr->io_lock);
if (status_reg & TWA_STATUS_COMMAND_QUEUE_FULL) {
@ -324,9 +306,6 @@ tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle,
}
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, req_pkt
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL) {
tw_cli_dbg_printf(2, ctlr_handle, tw_osl_cur_func(),
"Out of request context packets: returning busy");
@ -335,17 +314,6 @@ tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle,
}
req_handle->cl_req_ctxt = req;
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = req_pkt->dma_mem;
req->cmd_pkt_phys = req_pkt->dma_mem_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->req_handle = req_handle;
req->orig_req = req_pkt;
req->tw_cli_callback = tw_cli_complete_io;
@ -725,7 +693,7 @@ tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 cmd, TW_VOID *buf)
TWA_CURRENT_FW_BUILD(ctlr->arch_id);
comp_pkt.driver_srl_low = TWA_BASE_FW_SRL;
comp_pkt.driver_branch_low = TWA_BASE_FW_BRANCH;
comp_pkt.driver_build_high = TWA_BASE_FW_BUILD;
comp_pkt.driver_build_low = TWA_BASE_FW_BUILD;
comp_pkt.fw_on_ctlr_srl = ctlr->fw_on_ctlr_srl;
comp_pkt.fw_on_ctlr_branch = ctlr->fw_on_ctlr_branch;
comp_pkt.fw_on_ctlr_build = ctlr->fw_on_ctlr_build;
@ -781,9 +749,6 @@ tw_cli_get_param(struct tw_cli_ctlr_context *ctlr, TW_INT32 table_id,
/* Get a request packet. */
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_CL_NULL
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL)
goto out;
@ -793,17 +758,6 @@ tw_cli_get_param(struct tw_cli_ctlr_context *ctlr, TW_INT32 table_id,
goto out;
}
ctlr->state |= TW_CLI_CTLR_STATE_INTERNAL_REQ_BUSY;
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = ctlr->cmd_pkt_buf;
req->cmd_pkt_phys = ctlr->cmd_pkt_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->data = ctlr->internal_req_data;
req->data_phys = ctlr->internal_req_data_phys;
req->length = TW_CLI_SECTOR_SIZE;
@ -914,9 +868,6 @@ tw_cli_set_param(struct tw_cli_ctlr_context *ctlr, TW_INT32 table_id,
/* Get a request packet. */
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_CL_NULL
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL)
goto out;
@ -926,17 +877,6 @@ tw_cli_set_param(struct tw_cli_ctlr_context *ctlr, TW_INT32 table_id,
goto out;
}
ctlr->state |= TW_CLI_CTLR_STATE_INTERNAL_REQ_BUSY;
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = ctlr->cmd_pkt_buf;
req->cmd_pkt_phys = ctlr->cmd_pkt_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->data = ctlr->internal_req_data;
req->data_phys = ctlr->internal_req_data_phys;
req->length = TW_CLI_SECTOR_SIZE;
@ -1232,7 +1172,8 @@ tw_cli_soft_reset(struct tw_cli_ctlr_context *ctlr)
TW_CLI_SOFT_RESET(ctlr_handle);
if (ctlr->device_id == TW_CL_DEVICE_ID_9K_X) {
if ((ctlr->device_id == TW_CL_DEVICE_ID_9K_X) ||
(ctlr->device_id == TW_CL_DEVICE_ID_9K_E)) {
/*
* There's a hardware bug in the G133 ASIC, which can lead to
* PCI parity errors and hangs, if the host accesses any
@ -1406,22 +1347,9 @@ tw_cli_get_aen(struct tw_cli_ctlr_context *ctlr)
tw_cli_dbg_printf(4, ctlr->ctlr_handle, tw_osl_cur_func(), "entered");
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_CL_NULL
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL)
return(TW_OSL_EBUSY);
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = ctlr->cmd_pkt_buf;
req->cmd_pkt_phys = ctlr->cmd_pkt_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
req->flags |= TW_CLI_REQ_FLAGS_9K;
req->tw_cli_callback = tw_cli_aen_callback;

3
sys/dev/twa/tw_cl_ioctl.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/

53
sys/dev/twa/tw_cl_misc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -314,24 +315,11 @@ tw_cli_drain_aen_queue(struct tw_cli_ctlr_context *ctlr)
for (;;) {
if ((req = tw_cli_get_request(ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_CL_NULL
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)) == TW_CL_NULL) {
error = TW_OSL_EBUSY;
break;
}
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->cmd_pkt = ctlr->cmd_pkt_buf;
req->cmd_pkt_phys = ctlr->cmd_pkt_phys;
tw_osl_memzero(req->cmd_pkt,
sizeof(struct tw_cl_command_header) +
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
req->tw_cli_callback = TW_CL_NULL;
if ((error = tw_cli_send_scsi_cmd(req,
@ -601,31 +589,12 @@ tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle,
*/
struct tw_cli_req_context *
tw_cli_get_request(struct tw_cli_ctlr_context *ctlr
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, struct tw_cl_req_packet *req_pkt
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
)
{
struct tw_cli_req_context *req;
tw_cli_dbg_printf(4, ctlr->ctlr_handle, tw_osl_cur_func(), "entered");
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
if (req_pkt) {
if (ctlr->num_free_req_ids == 0)
return(TW_CL_NULL);
ctlr->num_free_req_ids--;
req = (struct tw_cli_req_context *)(req_pkt->non_dma_mem);
req->ctlr = ctlr;
req->request_id = ctlr->free_req_ids[ctlr->free_req_head];
ctlr->busy_reqs[req->request_id] = req;
ctlr->free_req_head = (ctlr->free_req_head + 1) %
(ctlr->max_simult_reqs - 1);
} else
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
{
/* Get a free request packet. */
req = tw_cli_req_q_remove_head(ctlr, TW_CLI_FREE_Q);
@ -643,8 +612,6 @@ tw_cli_get_request(struct tw_cli_ctlr_context *ctlr
req->orig_req = TW_CL_NULL;
req->tw_cli_callback = TW_CL_NULL;
#ifndef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
/*
* Look at the status field in the command packet to see how
* it completed the last time it was used, and zero out only
@ -659,7 +626,6 @@ tw_cli_get_request(struct tw_cli_ctlr_context *ctlr
tw_osl_memzero(&(req->cmd_pkt->command),
28 /* max bytes before sglist */);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
}
return(req);
}
@ -843,13 +809,14 @@ tw_cli_check_ctlr_state(struct tw_cli_ctlr_context *ctlr, TW_UINT32 status_reg)
}
if (status_reg & TWA_STATUS_QUEUE_ERROR_INTERRUPT) {
tw_cl_create_event(ctlr_handle, TW_CL_TRUE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT,
0x1305, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Controller queue error: clearing... ",
"status reg = 0x%x %s",
status_reg,
tw_cli_describe_bits(status_reg, desc));
if (ctlr->device_id != TW_CL_DEVICE_ID_9K_E)
tw_cl_create_event(ctlr_handle, TW_CL_TRUE,
TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT,
0x1305, 0x1, TW_CL_SEVERITY_ERROR_STRING,
"Controller queue error: clearing... ",
"status reg = 0x%x %s",
status_reg,
tw_cli_describe_bits(status_reg, desc));
TW_CLI_WRITE_CONTROL_REGISTER(ctlr->ctlr_handle,
TWA_CONTROL_CLEAR_QUEUE_ERROR);
}

70
sys/dev/twa/tw_cl_share.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -45,9 +46,6 @@
* and defined by CL.
*/
#define TW_CL_VERSION_STRING "1.00.01.011"
#define TW_CL_NULL ((TW_VOID *)0)
#define TW_CL_TRUE 1
#define TW_CL_FALSE 0
@ -55,6 +53,7 @@
#define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */
#define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */
#define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */
#define TW_CL_DEVICE_ID_9K_E 0x1004 /* 9000 PCIe series device id */
#define TW_CL_BAR_TYPE_IO 1 /* I/O base address */
#define TW_CL_BAR_TYPE_MEM 2 /* memory base address */
@ -64,7 +63,7 @@
#define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support
-- enclosure target id is 64 */
#else /* TW_OSL_ENCLOSURE_SUPPORT */
#define TW_CL_MAX_NUM_UNITS 16 /* max # of units we support */
#define TW_CL_MAX_NUM_UNITS 32 /* max # of units we support */
#endif /* TW_OSL_ENCLOSURE_SUPPORT */
#define TW_CL_MAX_NUM_LUNS 16 /* max # of LUN's we support */
@ -86,7 +85,6 @@
#define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */
#define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */
#define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */
#define TW_CL_FLASH_FIRMWARE (1<<4) /* Flash firmware */
#define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */
/* Possible error values from the Common Layer. */
@ -101,9 +99,7 @@
/* Possible values of req_pkt->flags */
#ifndef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
#define TW_CL_REQ_RETRY_ON_BUSY (1<<0)
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
#define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1)
@ -184,19 +180,6 @@ struct tw_cl_req_packet {
TW_UINT32 *num_sgl_entries);
/* OSL callback to get SG list. */
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
TW_VOID *dma_mem;
TW_UINT64 dma_mem_phys;
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
TW_VOID *non_dma_mem;
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
union {
struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */
struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/
@ -496,39 +479,6 @@ extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src);
extern TW_INT32 tw_osl_strlen(TW_VOID *str);
#endif
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
#ifndef tw_osl_sync_io_block
/* Block new I/O requests from being sent by the OS Layer. */
extern TW_VOID tw_osl_sync_io_block(struct tw_cl_ctlr_handle *ctlr_handle,
TW_SYNC_HANDLE *sync_handle);
#endif
#ifndef tw_osl_sync_io_unblock
/* Allow new I/O requests from the OS Layer. */
extern TW_VOID tw_osl_sync_io_unblock(struct tw_cl_ctlr_handle *ctlr_handle,
TW_SYNC_HANDLE *sync_handle);
#endif
#ifndef tw_osl_sync_isr_block
/* Block the ISR from being called by the OS Layer. */
extern TW_VOID tw_osl_sync_isr_block(struct tw_cl_ctlr_handle *ctlr_handle,
TW_SYNC_HANDLE *sync_handle);
#endif
#ifndef tw_osl_sync_isr_unblock
/* Allow calls to the ISR from the OS Layer. */
extern TW_VOID tw_osl_sync_isr_unblock(struct tw_cl_ctlr_handle *ctlr_handle,
TW_SYNC_HANDLE *sync_handle);
#endif
#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */
#ifndef tw_osl_vsprintf
/* Standard vsprintf. */
extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap);
@ -591,15 +541,6 @@ extern TW_INT32 tw_cl_get_mem_requirements(
TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
#ifdef TW_OSL_FLASH_FIRMWARE
, TW_UINT32 *flash_dma_mem_size
#endif /* TW_OSL_FLASH_FIRMWARE */
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
, TW_UINT32 *per_req_dma_mem_size
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
, TW_UINT32 *per_req_non_dma_mem_size
#endif /* TW_OSL_N0N_DMA_MEM_ALLOC_PER_REQUEST */
);
@ -613,9 +554,6 @@ extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem,
TW_UINT64 dma_mem_phys
#ifdef TW_OSL_FLASH_FIRMWARE
, TW_VOID *flash_dma_mem, TW_UINT64 flash_dma_mem_phys
#endif /* TW_OSL_FLASH_FIRMWARE */
);

12
sys/dev/twa/tw_osl.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -133,11 +134,6 @@ struct twa_softc {
TW_VOID *non_dma_mem;
TW_VOID *dma_mem;
TW_UINT64 dma_mem_phys;
#ifdef TW_OSL_FLASH_FIRMWARE
TW_VOID *flash_dma_mem;
TW_UINT64 flash_dma_mem_phys;
#endif /* TW_OSL_FLASH_FIRMWARE */
/* Request queues and arrays. */
struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
@ -164,10 +160,6 @@ struct twa_softc {
bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
#ifdef TW_OSL_FLASH_FIRMWARE
bus_dma_tag_t flash_tag;/* DMA tag for CL's fw flash mem */
bus_dmamap_t flash_map;/* DMA map for CL's fw flash mem */
#endif /* TW_OSL_FLASH_FIRMWARE */
struct resource *irq_res; /* interrupt resource */
TW_INT32 irq_res_id; /* register resource id */
TW_VOID *intr_handle; /* interrupt handle */

10
sys/dev/twa/tw_osl_cam.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -129,6 +130,7 @@ tw_osli_cam_attach(struct twa_softc *sc)
0x2102,
"Failed to register the bus",
ENXIO);
mtx_unlock(&Giant);
return(ENXIO);
}
@ -146,6 +148,7 @@ tw_osli_cam_attach(struct twa_softc *sc)
0x2103,
"Failed to create path",
ENXIO);
mtx_unlock(&Giant);
return(ENXIO);
}
@ -594,8 +597,11 @@ tw_osli_request_bus_scan(struct twa_softc *sc)
bzero(ccb, sizeof(union ccb));
mtx_lock(&Giant);
if (xpt_create_path(&path, xpt_periph, cam_sim_path(sc->sim),
CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP)
CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
free(ccb, M_TEMP);
mtx_unlock(&Giant);
return(EIO);
}
xpt_setup_ccb(&ccb->ccb_h, path, 5);
ccb->ccb_h.func_code = XPT_SCAN_BUS;

3
sys/dev/twa/tw_osl_externs.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/

138
sys/dev/twa/tw_osl_freebsd.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* Copyright (c) 2000 Michael Smith
* Copyright (c) 2000 BSDi
@ -33,6 +33,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -209,9 +210,8 @@ static driver_t twa_pci_driver = {
};
DRIVER_MODULE(twa, pci, twa_pci_driver, twa_devclass, 0, 0);
MODULE_DEPEND(twa, pci, 1, 1, 1);
MODULE_DEPEND(twa, cam, 1, 1, 1);
MODULE_DEPEND(twa, pci, 1, 1, 1);
/*
@ -396,9 +396,6 @@ twa_attach(device_t dev)
TW_OSLI_MAX_NUM_IOS, TW_OSLI_MAX_NUM_AENS,
sc->non_dma_mem, sc->dma_mem,
sc->dma_mem_phys
#ifdef TW_OSL_FLASH_FIRMWARE
, sc->flash_dma_mem, sc->flash_dma_mem_phys
#endif /* TW_OSL_FLASH_FIRMWARE */
))) {
tw_osli_printf(sc, "error = %d",
TW_CL_SEVERITY_ERROR_STRING,
@ -410,23 +407,6 @@ twa_attach(device_t dev)
return(error);
}
#ifdef TW_OSL_FLASH_FIRMWARE
/* Free any memory allocated for firmware flashing. */
if (sc->flash_dma_mem) {
bus_dmamap_unload(sc->flash_tag, sc->flash_map);
bus_dmamem_free(sc->flash_tag, sc->flash_dma_mem,
sc->flash_map);
}
if (sc->flash_tag)
bus_dma_tag_destroy(sc->flash_tag);
/*
* Set flash_tag and flash_dma_mem to 0, so we don't try freeing them
* again, later.
*/
sc->flash_tag = 0;
sc->flash_dma_mem = 0;
#endif /* TW_OSL_FLASH_FIRMWARE */
/* Create the control device. */
sc->ctrl_dev = make_dev(&twa_cdevsw, device_get_unit(sc->bus_dev),
UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR,
@ -465,12 +445,6 @@ tw_osli_alloc_mem(struct twa_softc *sc)
TW_UINT32 max_sg_elements;
TW_UINT32 non_dma_mem_size;
TW_UINT32 dma_mem_size;
#ifdef TW_OSL_FLASH_FIRMWARE
TW_UINT32 flash_dma_mem_size;
#endif /* TW_OSL_FLASH_FIRMWARE */
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
TW_UINT32 per_req_dma_mem_size;
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
TW_INT32 error;
TW_INT32 i;
@ -478,9 +452,6 @@ tw_osli_alloc_mem(struct twa_softc *sc)
sc->flags |= (sizeof(bus_addr_t) == 8) ? TW_CL_64BIT_ADDRESSES : 0;
sc->flags |= (sizeof(bus_size_t) == 8) ? TW_CL_64BIT_SG_LENGTH : 0;
#ifdef TW_OSL_FLASH_FIRMWARE
sc->flags |= TW_CL_FLASH_FIRMWARE;
#endif /* TW_OSL_FLASH_FIRMWARE */
#ifdef TW_OSLI_DEFERRED_INTR_USED
sc->flags |= TW_CL_DEFERRED_INTR_USED;
#endif /* TW_OSLI_DEFERRED_INTR_USED */
@ -492,12 +463,6 @@ tw_osli_alloc_mem(struct twa_softc *sc)
sc->device_id, TW_OSLI_MAX_NUM_IOS, TW_OSLI_MAX_NUM_AENS,
&(sc->alignment), &(sc->sg_size_factor),
&non_dma_mem_size, &dma_mem_size
#ifdef TW_OSL_FLASH_FIRMWARE
, &flash_dma_mem_size
#endif /* TW_OSL_FLASH_FIRMWARE */
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
, &per_req_dma_mem_size
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
))) {
tw_osli_printf(sc, "error = %d",
TW_CL_SEVERITY_ERROR_STRING,
@ -549,10 +514,6 @@ tw_osli_alloc_mem(struct twa_softc *sc)
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
(TW_OSLI_MAX_NUM_IOS *
per_req_dma_mem_size) +
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
dma_mem_size, /* maxsize */
1, /* nsegments */
BUS_SPACE_MAXSIZE, /* maxsegsize */
@ -590,53 +551,6 @@ tw_osli_alloc_mem(struct twa_softc *sc)
dma_mem_size, twa_map_load_callback,
&sc->dma_mem_phys, 0);
#ifdef TW_OSL_FLASH_FIRMWARE
/*
* Create a dma tag for Common Layer's DMA'able memory,
* used to flash firmware (flash_dma_mem).
*/
if (bus_dma_tag_create(sc->parent_tag, /* parent */
sc->alignment, /* alignment */
0, /* boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
flash_dma_mem_size, /* maxsize */
1, /* nsegments */
flash_dma_mem_size, /* maxsegsize */
0, /* flags */
NULL, /* lockfunc */
NULL, /* lockfuncarg */
&sc->flash_tag /* tag */)) {
tw_osli_printf(sc, "error = %d",
TW_CL_SEVERITY_ERROR_STRING,
TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER,
0x200D,
"Can't allocate DMA tag for Common Layer's "
"firmware flash memory",
ENOMEM);
return(ENOMEM);
}
if (bus_dmamem_alloc(sc->flash_tag, &sc->flash_dma_mem,
BUS_DMA_NOWAIT, &sc->flash_map)) {
tw_osli_printf(sc, "error = %d",
TW_CL_SEVERITY_ERROR_STRING,
TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER,
0x200E,
"Can't allocate DMA'able memory for Common Layer's "
"firmware flash",
ENOMEM);
return(ENOMEM);
}
bus_dmamap_load(sc->flash_tag, sc->flash_map, sc->flash_dma_mem,
flash_dma_mem_size, twa_map_load_callback,
&sc->flash_dma_mem_phys, 0);
#endif /* TW_OSL_FLASH_FIRMWARE */
/*
* Create a dma tag for data buffers; size will be the maximum
* possible I/O size (128kB).
@ -733,27 +647,10 @@ tw_osli_alloc_mem(struct twa_softc *sc)
return(ENOMEM);
}
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
req->req_pkt.dma_mem = ((TW_INT8 *)(sc->dma_mem)) +
(i * per_req_dma_mem_size);
req->req_pkt.dma_mem_phys = sc->dma_mem_phys +
(i * per_req_dma_mem_size);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
/* Insert request into the free queue. */
tw_osli_req_q_insert_tail(req, TW_OSLI_FREE_Q);
}
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
sc->dma_mem = ((TW_INT8 *)(sc->dma_mem)) +
(TW_OSLI_MAX_NUM_IOS * per_req_dma_mem_size);
sc->dma_mem_phys += (TW_OSLI_MAX_NUM_IOS * per_req_dma_mem_size);
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
return(0);
}
@ -809,22 +706,6 @@ tw_osli_free_resources(struct twa_softc *sc)
tw_osli_dbg_dprintf(1, sc,
"dma_tag_destroy(cmd) returned %d", error);
#ifdef TW_OSL_FLASH_FIRMWARE
if (sc->flash_dma_mem) {
/* In case this piece of memory has already been freed. */
bus_dmamap_unload(sc->flash_tag, sc->flash_map);
bus_dmamem_free(sc->flash_tag, sc->flash_dma_mem,
sc->flash_map);
}
if (sc->flash_tag)
if ((error = bus_dma_tag_destroy(sc->flash_tag)))
tw_osli_dbg_dprintf(1, sc,
"dma_tag_destroy(flash) returned %d", error);
#endif /* TW_OSL_FLASH_FIRMWARE */
if (sc->dma_tag)
if ((error = bus_dma_tag_destroy(sc->dma_tag)))
tw_osli_dbg_dprintf(1, sc,
@ -1330,21 +1211,8 @@ tw_osli_get_request(struct twa_softc *sc)
req->error_code = 0;
req->orig_req = NULL;
#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
/* Don't zero dma_mem & dma_mem_phys in req_pkt. */
req->req_pkt.cmd = 0;
req->req_pkt.flags = 0;
req->req_pkt.status = 0;
req->req_pkt.tw_osl_callback = NULL;
bzero(&(req->req_pkt.gen_req_pkt),
sizeof(req->req_pkt.gen_req_pkt));
#else /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
bzero(&(req->req_pkt), sizeof(struct tw_cl_req_packet));
#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
}
return(req);
}

3
sys/dev/twa/tw_osl_includes.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/

3
sys/dev/twa/tw_osl_inline.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/

3
sys/dev/twa/tw_osl_ioctl.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/

10
sys/dev/twa/tw_osl_share.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/
@ -70,15 +71,11 @@
#define TW_OSL_DEBUG TWA_DEBUG
#endif
#ifdef TWA_FLASH_FIRMWARE
#define TW_OSL_FLASH_FIRMWARE
#endif
#ifdef TWA_ENCLOSURE_SUPPORT
#define TW_OSL_ENCLOSURE_SUPPORT
#endif
#define TW_OSL_DRIVER_VERSION_STRING "3.70.02.012"
#define TW_OSL_DRIVER_VERSION_STRING "3.60.03.006"
#define TW_OSL_CAN_SLEEP
@ -86,7 +83,6 @@
typedef TW_VOID *TW_SLEEP_HANDLE;
#endif /* TW_OSL_CAN_SLEEP */
/*#define TW_OSL_DMA_MEM_ALLOC_PER_REQUEST*/
#define TW_OSL_PCI_CONFIG_ACCESSIBLE
#if _BYTE_ORDER == _BIG_ENDIAN

3
sys/dev/twa/tw_osl_types.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
* Copyright (c) 2004-05 Vinod Kashyap.
* All rights reserved.
*
@ -31,6 +31,7 @@
* AMCC'S 3ware driver for 9000 series storage controllers.
*
* Author: Vinod Kashyap
* Modifications by: Adam Radford
*/

31
sys/modules/twa/Makefile
View File

@ -1,6 +1,6 @@
# $FreeBSD$
#
# Copyright (c) 2004 Applied Micro Circuits Corporation.
# Copyright (c) 2004-06 Applied Micro Circuits Corporation.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@ -29,31 +29,9 @@
# 3ware driver for 9000 series storage controllers.
#
# Author: Vinod Kashyap
# Modifications by: Adam Radford
#
#
# In the line following this comment, a value of 0 on the right hand
# side will not cause firmware to be bundled. Change this value to 1
# to bundle the firmware with the driver, which may be flashed onto
# the controller, if the firmware on the controller is older than the
# one bundled, and needs to be upgraded. The size of the driver will
# increase significantly (to over 500kB) if this option is selected.
# Typically, the firmware image bundled (in tw_cl_fwimg.c) corresponds
# to the latest controller architecture as of the date of the release.
# If the firmware for an earlier controller architecture needs to be
# flashed, the (older) driver with the appropriate firmware image
# bundled can be downloaded from the 3ware website, used to flash the
# firmware, and then the newer driver can be switched to. Alternatively,
# the appropriate firmware image (tw_cl_fwimg.c) from the older driver can
# be used to re-build the newer driver. In this case, the branch
# (TWA_CURRENT_FW_BRANCH_*) and build (TWA_CURRENT_FW_BUILD_*) numbers for
# the bundled firmware need to be appropriately updated in tw_cl_fwif.h
# before building the driver.
#
TWA_FLASH_FIRMWARE?=0
KMOD = twa
.PATH: ${.CURDIR}/../../dev/${KMOD}
SRCS= tw_osl_freebsd.c tw_osl_cam.c \
@ -66,9 +44,4 @@ SRCS= tw_osl_freebsd.c tw_osl_cam.c \
#CFLAGS+= -DTWA_DEBUG=0
CFLAGS+= -I${.CURDIR}/../../dev/${KMOD}
.if $(TWA_FLASH_FIRMWARE) != 0
CFLAGS+= -DTWA_FLASH_FIRMWARE
SRCS+= tw_cl_fwimg.c
.endif
.include <bsd.kmod.mk>