Switch to using PAs rather than VAs for the addresses we map for
devices. This is a nop, except for what's reported by atmelbus for the resources. It would be nice if we could dymanically allocated these things, but the pmap_mapdev panics if we don't keep the static mappings, so we still need to play the carefully allocate VA space between all supported SoC game. User's with their own devices may need to make adjustments.
This commit is contained in:
Warner Losh
parent
b35ac06804
commit
4587b6e9fd
@ -260,7 +260,6 @@ static int
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at91_attach(device_t dev)
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{
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struct at91_softc *sc = device_get_softc(dev);
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const struct arm_devmap_entry *pdevmap;
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int i;
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arm_post_filter = at91_eoi;
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@ -281,11 +280,15 @@ at91_attach(device_t dev)
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sc->sc_mem_rman.rm_descr = "AT91 Memory";
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if (rman_init(&sc->sc_mem_rman) != 0)
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panic("at91_attach: failed to set up memory rman");
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for (pdevmap = at91_devmap; pdevmap->pd_va != 0; pdevmap++) {
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if (rman_manage_region(&sc->sc_mem_rman, pdevmap->pd_va,
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pdevmap->pd_va + pdevmap->pd_size - 1) != 0)
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panic("at91_attach: failed to set up memory rman");
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}
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/*
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* Manage the physical space, defined as being everything that isn't
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* DRAM.
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*/
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if (rman_manage_region(&sc->sc_mem_rman, 0, PHYSADDR - 1) != 0)
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panic("at91_attach: failed to set up memory rman");
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if (rman_manage_region(&sc->sc_mem_rman, PHYSADDR + (256 << 20),
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0xfffffffful) != 0)
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panic("at91_attach: failed to set up memory rman");
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/*
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* Setup the interrupt table.
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@ -330,6 +333,7 @@ at91_alloc_resource(device_t dev, device_t child, int type, int *rid,
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struct resource_list_entry *rle;
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struct at91_ivar *ivar = device_get_ivars(child);
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struct resource_list *rl = &ivar->resources;
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bus_space_handle_t bsh;
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if (device_get_parent(child) != dev)
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return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
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@ -355,8 +359,10 @@ at91_alloc_resource(device_t dev, device_t child, int type, int *rid,
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rle->res = rman_reserve_resource(&sc->sc_mem_rman,
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start, end, count, flags, child);
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if (rle->res != NULL) {
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bus_space_map(&at91_bs_tag, start,
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rman_get_size(rle->res), 0, &bsh);
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rman_set_bustag(rle->res, &at91_bs_tag);
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rman_set_bushandle(rle->res, start);
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rman_set_bushandle(rle->res, bsh);
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}
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break;
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}
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@ -538,8 +544,14 @@ at91_add_child(device_t dev, int prio, const char *name, int unit,
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bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
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if (irq2 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
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if (addr != 0 && addr < AT91_BASE)
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addr += AT91_BASE;
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/*
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* Special case for on-board devices. These have their address
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* defined relative to AT91_PA_BASE in all the register files we
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* have. We could change this, but that's a lot of effort which
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* will be obsoleted when FDT arrives.
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*/
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if (addr != 0 && addr < 0x10000000 && addr >= 0x0f000000)
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addr += AT91_PA_BASE;
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if (addr != 0)
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bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
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}
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@ -146,6 +146,7 @@ const struct arm_devmap_entry at91_devmap[] = {
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* There's a notion that we should do the rest of these lazily. */
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/*
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* We can't just map the OHCI registers VA == PA, because
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* AT91xx_xxx_BASE belongs to the userland address space.
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@ -163,16 +164,16 @@ const struct arm_devmap_entry at91_devmap[] = {
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* on this chip select for a VA/PA mapping.
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*/
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/* Internal Memory 1MB */
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AT91RM92_OHCI_VA_BASE,
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AT91RM92_OHCI_BASE,
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AT91RM92_OHCI_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{
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/* CompactFlash controller. Portion of EBI CS4 1MB */
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AT91RM92_CF_VA_BASE,
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AT91RM92_CF_BASE,
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AT91RM92_CF_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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@ -183,16 +184,16 @@ const struct arm_devmap_entry at91_devmap[] = {
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*/
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{
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/* Internal Memory 1MB */
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AT91SAM9G20_OHCI_VA_BASE,
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AT91SAM9G20_OHCI_BASE,
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AT91SAM9G20_OHCI_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{
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/* EBI CS3 256MB */
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AT91SAM9G20_NAND_VA_BASE,
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AT91SAM9G20_NAND_BASE,
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AT91SAM9G20_NAND_PA_BASE,
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AT91SAM9G20_NAND_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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@ -202,8 +203,8 @@ const struct arm_devmap_entry at91_devmap[] = {
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*/
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{
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/* Internal Memory 1MB */
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AT91SAM9G45_OHCI_VA_BASE,
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AT91SAM9G45_OHCI_BASE,
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AT91SAM9G45_OHCI_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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@ -255,12 +255,12 @@
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* other * soc's so phyical and vm address
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* mapping are unique. XXX
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*/
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#define AT91RM92_OHCI_BASE 0xdfe00000
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#define AT91RM92_OHCI_PA_BASE 0x00300000
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#define AT91RM92_OHCI_VA_BASE 0xdfe00000
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#define AT91RM92_OHCI_BASE 0x00300000
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#define AT91RM92_OHCI_SIZE 0x00100000
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#define AT91RM92_CF_BASE 0xdfd00000
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#define AT91RM92_CF_PA_BASE 0x51400000
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#define AT91RM92_CF_VA_BASE 0xdfd00000
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#define AT91RM92_CF_BASE 0x51400000
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#define AT91RM92_CF_SIZE 0x00100000
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/* SDRAMC */
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@ -252,14 +252,13 @@
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* other * soc's so phyical and vm address
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* mapping are unique. XXX
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*/
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#define AT91SAM9G20_OHCI_BASE 0xdfc00000
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#define AT91SAM9G20_OHCI_PA_BASE 0x00500000
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#define AT91SAM9G20_OHCI_SIZE 0x00100000
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#define AT91SAM9G20_NAND_BASE 0xe0000000
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#define AT91SAM9G20_NAND_PA_BASE 0x40000000
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#define AT91SAM9G20_NAND_SIZE 0x10000000
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#define AT91SAM9G20_OHCI_VA_BASE 0xdfc00000
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#define AT91SAM9G20_OHCI_BASE 0x00500000
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#define AT91SAM9G20_OHCI_SIZE 0x00100000
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#define AT91SAM9G20_NAND_VA_BASE 0xe0000000
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#define AT91SAM9G20_NAND_BASE 0x40000000
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#define AT91SAM9G20_NAND_SIZE 0x10000000
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/* SDRAMC */
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#define AT91SAM9G20_SDRAMC_BASE 0xfffea00
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@ -243,13 +243,13 @@
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* other * soc's so phyical and vm address
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* mapping are unique. XXX
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*/
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#define AT91SAM9G45_OHCI_BASE 0xdfb00000
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#define AT91SAM9G45_OHCI_PA_BASE 0x00700000
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#define AT91SAM9G45_OHCI_SIZE 0x00100000
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#define AT91SAM9G45_OHCI_VA_BASE 0xdfb00000
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#define AT91SAM9G45_OHCI_BASE 0x00700000
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#define AT91SAM9G45_OHCI_SIZE 0x00100000
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#define AT91SAM9G45_NAND_BASE 0xe0000000
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#define AT91SAM9G45_NAND_PA_BASE 0x40000000
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#define AT91SAM9G45_NAND_SIZE 0x10000000
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#define AT91SAM9G45_NAND_VA_BASE 0xe0000000
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#define AT91SAM9G45_NAND_BASE 0x40000000
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#define AT91SAM9G45_NAND_SIZE 0x10000000
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/* DDRSDRC */
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