diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index 1a251208cfd6..1b731821889e 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -255,6 +255,7 @@ initializecpu(void)
 {
 	uint64_t msr;
 	uint32_t cr4;
+	u_int r[4];
 
 	cr4 = rcr4();
 	if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
@@ -317,6 +318,14 @@ initializecpu(void)
 	if ((amd_feature & AMDID_RDTSCP) != 0 ||
 	    (cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0)
 		wrmsr(MSR_TSC_AUX, cpu_auxmsr());
+
+	if (cpu_high >= 0x1a) {
+		cpuid_count(0x1a, 0, r);
+		if ((r[0] & CPUID_HYBRID_CORE_MASK) ==
+		    CPUID_HYBRID_SMALL_CORE) {
+			PCPU_SET(small_core, 1);
+		}
+	}
 }
 
 void
diff --git a/sys/amd64/include/pcpu.h b/sys/amd64/include/pcpu.h
index 8dcf51cc71c6..70f008fe835a 100644
--- a/sys/amd64/include/pcpu.h
+++ b/sys/amd64/include/pcpu.h
@@ -99,7 +99,8 @@ _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line");
 	uint32_t pc_smp_tlb_gen;					\
 	u_int	pc_smp_tlb_op;						\
 	uint64_t pc_ucr3_load_mask;					\
-	char	__pad[2916]		/* pad to UMA_PCPU_ALLOC_SIZE */
+	u_int	pc_small_core;						\
+	char	__pad[2912]		/* pad to UMA_PCPU_ALLOC_SIZE */
 
 #define	PC_DBREG_CMD_NONE	0
 #define	PC_DBREG_CMD_LOAD	1
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
index 0185317dbd38..395338b4a4b4 100644
--- a/sys/x86/include/specialreg.h
+++ b/sys/x86/include/specialreg.h
@@ -490,6 +490,11 @@
 #define	CPUID_STDEXT3_CORE_CAP		0x40000000
 #define	CPUID_STDEXT3_SSBD		0x80000000
 
+/* CPUID_HYBRID_ID leaf 0x1a */
+#define	CPUID_HYBRID_CORE_MASK	0xff000000
+#define	CPUID_HYBRID_SMALL_CORE	0x20000000
+#define	CPUID_HYBRID_LARGE_CORE	0x40000000
+
 /* MSR IA32_ARCH_CAP(ABILITIES) bits */
 #define	IA32_ARCH_CAP_RDCL_NO	0x00000001
 #define	IA32_ARCH_CAP_IBRS_ALL	0x00000002