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According to Section D5.10.3 "Maintenance requirements on changing System

Browse Source 
register values" of the architecture manual, an isb instruction should be
executed after updating ttbr0_el1 and before invalidating the TLB.  The
lack of this instruction in pmap_activate() appears to be the reason why
andrew@ and I have observed an unexpected TLB entry for an invalid PTE on
entry to pmap_enter_quick_locked().  Thus, we should now be able to revert
the workaround committed in r349442.

Reviewed by:	markj
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D20904
This commit is contained in:
Alan Cox 2019-07-11 02:43:23 +00:00
parent 32e42e4a89
commit 46a7f2ebd4
2 changed files with 6 additions and 2 deletions
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2
sys/arm64/arm64/efirt_machdep.c
View File

@ -239,6 +239,7 @@ efi_arch_enter(void)
__asm __volatile(
"msr ttbr0_el1, %0 \n"
"isb \n"
"dsb ishst \n"
"tlbi vmalle1is \n"
"dsb ish \n"
@ -266,6 +267,7 @@ efi_arch_leave(void)
td = curthread;
__asm __volatile(
"msr ttbr0_el1, %0 \n"
"isb \n"
"dsb ishst \n"
"tlbi vmalle1is \n"
"dsb ish \n"

6
sys/arm64/arm64/pmap.c
View File

@ -5484,8 +5484,10 @@ pmap_activate(struct thread *td)
critical_enter();
pmap = vmspace_pmap(td->td_proc->p_vmspace);
td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
__asm __volatile("msr ttbr0_el1, %0" : :
"r"(td->td_proc->p_md.md_l0addr));
__asm __volatile(
"msr ttbr0_el1, %0 \n"
"isb \n"
: : "r"(td->td_proc->p_md.md_l0addr));
pmap_invalidate_all(pmap);
critical_exit();
}