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Style/whitespace cleanup in shared/common code.

Browse Source 
Differential Revision:	https://reviews.freebsd.org/D3159
Submitted by:	erj
MFC after:	2 weeks
This commit is contained in:
Sean Bruno 2015-08-24 16:32:57 +00:00
parent d1a0d267b7
commit 48600901a8
13 changed files with 309 additions and 338 deletions
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290
sys/dev/e1000/e1000_82541.c
View File

@ -49,34 +49,34 @@ static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
static s32 e1000_init_hw_82541(struct e1000_hw *hw);
static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
u16 *duplex);
u16 *duplex);
static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
bool active);
bool active);
static s32 e1000_setup_led_82541(struct e1000_hw *hw);
static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw);
static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
bool link_up);
bool link_up);
static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
static const u16 e1000_igp_cable_length_table[] =
{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
static const u16 e1000_igp_cable_length_table[] = {
5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10,
10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30,
40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60,
60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80,
80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100,
100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110,
110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120,
120, 120, 120, 120, 120, 120, 120, 120};
#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
(sizeof(e1000_igp_cable_length_table) / \
sizeof(e1000_igp_cable_length_table[0]))
(sizeof(e1000_igp_cable_length_table) / \
sizeof(e1000_igp_cable_length_table[0]))
/**
* e1000_init_phy_params_82541 - Init PHY func ptrs.
@ -89,23 +89,23 @@ static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
DEBUGFUNC("e1000_init_phy_params_82541");
phy->addr = 1;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->reset_delay_us = 10000;
phy->type = e1000_phy_igp;
phy->addr = 1;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->reset_delay_us = 10000;
phy->type = e1000_phy_igp;
/* Function Pointers */
phy->ops.check_polarity = e1000_check_polarity_igp;
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
phy->ops.get_info = e1000_get_phy_info_igp;
phy->ops.read_reg = e1000_read_phy_reg_igp;
phy->ops.reset = e1000_phy_hw_reset_82541;
phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
phy->ops.write_reg = e1000_write_phy_reg_igp;
phy->ops.power_up = e1000_power_up_phy_copper;
phy->ops.power_down = e1000_power_down_phy_copper_82541;
phy->ops.check_polarity = e1000_check_polarity_igp;
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
phy->ops.get_info = e1000_get_phy_info_igp;
phy->ops.read_reg = e1000_read_phy_reg_igp;
phy->ops.reset = e1000_phy_hw_reset_82541;
phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
phy->ops.write_reg = e1000_write_phy_reg_igp;
phy->ops.power_up = e1000_power_up_phy_copper;
phy->ops.power_down = e1000_power_down_phy_copper_82541;
ret_val = e1000_get_phy_id(hw);
if (ret_val)
@ -127,8 +127,8 @@ out:
**/
static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
s32 ret_val = E1000_SUCCESS;
struct e1000_nvm_info *nvm = &hw->nvm;
s32 ret_val = E1000_SUCCESS;
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
u16 size;
@ -152,28 +152,25 @@ static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
eecd &= ~E1000_EECD_SIZE;
break;
default:
nvm->type = eecd & E1000_EECD_TYPE
? e1000_nvm_eeprom_spi
: e1000_nvm_eeprom_microwire;
nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi
: e1000_nvm_eeprom_microwire;
break;
}
if (nvm->type == e1000_nvm_eeprom_spi) {
nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
? 16 : 8;
nvm->delay_usec = 1;
nvm->opcode_bits = 8;
nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
? 32 : 8;
nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;
nvm->delay_usec = 1;
nvm->opcode_bits = 8;
nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;
/* Function Pointers */
nvm->ops.acquire = e1000_acquire_nvm_generic;
nvm->ops.read = e1000_read_nvm_spi;
nvm->ops.release = e1000_release_nvm_generic;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.acquire = e1000_acquire_nvm_generic;
nvm->ops.read = e1000_read_nvm_spi;
nvm->ops.release = e1000_release_nvm_generic;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.valid_led_default = e1000_valid_led_default_generic;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.write = e1000_write_nvm_spi;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.write = e1000_write_nvm_spi;
/*
* nvm->word_size must be discovered after the pointers
@ -196,21 +193,19 @@ static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
nvm->word_size = 1 << size;
}
} else {
nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
? 8 : 6;
nvm->delay_usec = 50;
nvm->opcode_bits = 3;
nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
? 256 : 64;
nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;
nvm->delay_usec = 50;
nvm->opcode_bits = 3;
nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;
/* Function Pointers */
nvm->ops.acquire = e1000_acquire_nvm_generic;
nvm->ops.read = e1000_read_nvm_microwire;
nvm->ops.release = e1000_release_nvm_generic;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.acquire = e1000_acquire_nvm_generic;
nvm->ops.read = e1000_read_nvm_microwire;
nvm->ops.release = e1000_release_nvm_generic;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.valid_led_default = e1000_valid_led_default_generic;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.write = e1000_write_nvm_microwire;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.write = e1000_write_nvm_microwire;
}
out:
@ -390,11 +385,10 @@ static s32 e1000_init_hw_82541(struct e1000_hw *hw)
DEBUGOUT("Error initializing identification LED\n");
/* This is not fatal and we should not stop init due to this */
}
/* Storing the Speed Power Down value for later use */
ret_val = hw->phy.ops.read_reg(hw,
IGP01E1000_GMII_FIFO,
&dev_spec->spd_default);
ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
&dev_spec->spd_default);
if (ret_val)
goto out;
@ -423,7 +417,7 @@ static s32 e1000_init_hw_82541(struct e1000_hw *hw)
txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
/*
@ -447,7 +441,7 @@ out:
* Retrieve the current speed and duplex configuration.
**/
static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
u16 *duplex)
u16 *duplex)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
@ -549,6 +543,7 @@ static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
/* Earlier revs of the IGP phy require us to force MDI. */
if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
dev_spec->dsp_config = e1000_dsp_config_disabled;
@ -651,9 +646,8 @@ static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
* different link partner.
*/
ret_val = e1000_config_fc_after_link_up_generic(hw);
if (ret_val) {
if (ret_val)
DEBUGOUT("Error configuring flow control\n");
}
out:
return ret_val;
@ -671,7 +665,7 @@ out:
* gigabit link is achieved to improve link quality.
**/
static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
bool link_up)
bool link_up)
{
struct e1000_phy_info *phy = &hw->phy;
struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
@ -679,11 +673,11 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
u32 idle_errs = 0;
u16 phy_data, phy_saved_data, speed, duplex, i;
u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
{IGP01E1000_PHY_AGC_PARAM_A,
IGP01E1000_PHY_AGC_PARAM_B,
IGP01E1000_PHY_AGC_PARAM_C,
IGP01E1000_PHY_AGC_PARAM_D};
u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
IGP01E1000_PHY_AGC_PARAM_A,
IGP01E1000_PHY_AGC_PARAM_B,
IGP01E1000_PHY_AGC_PARAM_C,
IGP01E1000_PHY_AGC_PARAM_D};
DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
@ -708,16 +702,16 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ret_val = phy->ops.read_reg(hw,
dsp_reg_array[i],
&phy_data);
dsp_reg_array[i],
&phy_data);
if (ret_val)
goto out;
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
ret_val = phy->ops.write_reg(hw,
dsp_reg_array[i],
phy_data);
dsp_reg_array[i],
phy_data);
if (ret_val)
goto out;
}
@ -737,9 +731,8 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
for (i = 0; i < ffe_idle_err_timeout; i++) {
usec_delay(1000);
ret_val = phy->ops.read_reg(hw,
PHY_1000T_STATUS,
&phy_data);
ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
&phy_data);
if (ret_val)
goto out;
@ -748,8 +741,8 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
dev_spec->ffe_config = e1000_ffe_config_active;
ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_DSP_FFE,
IGP01E1000_PHY_DSP_FFE_CM_CP);
IGP01E1000_PHY_DSP_FFE,
IGP01E1000_PHY_DSP_FFE_CM_CP);
if (ret_val)
goto out;
break;
@ -757,7 +750,7 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
if (idle_errs)
ffe_idle_err_timeout =
FFE_IDLE_ERR_COUNT_TIMEOUT_100;
FFE_IDLE_ERR_COUNT_TIMEOUT_100;
}
} else {
if (dev_spec->dsp_config == e1000_dsp_config_activated) {
@ -765,9 +758,8 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
* Save off the current value of register 0x2F5B
* to be restored at the end of the routines.
*/
ret_val = phy->ops.read_reg(hw,
0x2F5B,
&phy_saved_data);
ret_val = phy->ops.read_reg(hw, 0x2F5B,
&phy_saved_data);
if (ret_val)
goto out;
@ -778,15 +770,14 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
msec_delay_irq(20);
ret_val = phy->ops.write_reg(hw,
0x0000,
IGP01E1000_IEEE_FORCE_GIG);
ret_val = phy->ops.write_reg(hw, 0x0000,
IGP01E1000_IEEE_FORCE_GIG);
if (ret_val)
goto out;
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ret_val = phy->ops.read_reg(hw,
dsp_reg_array[i],
&phy_data);
dsp_reg_array[i],
&phy_data);
if (ret_val)
goto out;
@ -794,24 +785,22 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
ret_val = phy->ops.write_reg(hw,
dsp_reg_array[i],
phy_data);
dsp_reg_array[i],
phy_data);
if (ret_val)
goto out;
}
ret_val = phy->ops.write_reg(hw,
0x0000,
IGP01E1000_IEEE_RESTART_AUTONEG);
ret_val = phy->ops.write_reg(hw, 0x0000,
IGP01E1000_IEEE_RESTART_AUTONEG);
if (ret_val)
goto out;
msec_delay_irq(20);
/* Now enable the transmitter */
ret_val = phy->ops.write_reg(hw,
0x2F5B,
phy_saved_data);
ret_val = phy->ops.write_reg(hw, 0x2F5B,
phy_saved_data);
if (ret_val)
goto out;
@ -838,21 +827,18 @@ static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
msec_delay_irq(20);
ret_val = phy->ops.write_reg(hw,
0x0000,
IGP01E1000_IEEE_FORCE_GIG);
ret_val = phy->ops.write_reg(hw, 0x0000,
IGP01E1000_IEEE_FORCE_GIG);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_DSP_FFE,
IGP01E1000_PHY_DSP_FFE_DEFAULT);
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
IGP01E1000_PHY_DSP_FFE_DEFAULT);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw,
0x0000,
IGP01E1000_IEEE_RESTART_AUTONEG);
ret_val = phy->ops.write_reg(hw, 0x0000,
IGP01E1000_IEEE_RESTART_AUTONEG);
if (ret_val)
goto out;
@ -889,11 +875,10 @@ static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
u16 i, data;
u16 cur_agc_value, agc_value = 0;
u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
{IGP01E1000_PHY_AGC_A,
IGP01E1000_PHY_AGC_B,
IGP01E1000_PHY_AGC_C,
IGP01E1000_PHY_AGC_D};
u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A,
IGP01E1000_PHY_AGC_B,
IGP01E1000_PHY_AGC_C,
IGP01E1000_PHY_AGC_D};
DEBUGFUNC("e1000_get_cable_length_igp_82541");
@ -929,12 +914,12 @@ static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
}
phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
IGP01E1000_AGC_RANGE)
? (e1000_igp_cable_length_table[agc_value] -
IGP01E1000_AGC_RANGE)
: 0;
IGP01E1000_AGC_RANGE)
? (e1000_igp_cable_length_table[agc_value] -
IGP01E1000_AGC_RANGE)
: 0;
phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
IGP01E1000_AGC_RANGE;
IGP01E1000_AGC_RANGE;
phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
@ -992,50 +977,48 @@ static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
*/
if (phy->smart_speed == e1000_smart_speed_on) {
ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
goto out;
} else if (phy->smart_speed == e1000_smart_speed_off) {
ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
goto out;
}
} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
data |= IGP01E1000_GMII_FLEX_SPD;
ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
if (ret_val)
goto out;
/* When LPLU is enabled, we should disable SmartSpeed */
ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
data);
}
out:
@ -1056,16 +1039,14 @@ static s32 e1000_setup_led_82541(struct e1000_hw *hw)
DEBUGFUNC("e1000_setup_led_82541");
ret_val = hw->phy.ops.read_reg(hw,
IGP01E1000_GMII_FIFO,
&dev_spec->spd_default);
ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
&dev_spec->spd_default);
if (ret_val)
goto out;
ret_val = hw->phy.ops.write_reg(hw,
IGP01E1000_GMII_FIFO,
(u16)(dev_spec->spd_default &
~IGP01E1000_GMII_SPD));
ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
(u16)(dev_spec->spd_default &
~IGP01E1000_GMII_SPD));
if (ret_val)
goto out;
@ -1089,9 +1070,8 @@ static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
DEBUGFUNC("e1000_cleanup_led_82541");
ret_val = hw->phy.ops.write_reg(hw,
IGP01E1000_GMII_FIFO,
dev_spec->spd_default);
ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
dev_spec->spd_default);
if (ret_val)
goto out;
@ -1178,14 +1158,12 @@ static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
u16 fused, fine, coarse;
/* Move to analog registers page */
hw->phy.ops.read_reg(hw,
IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
&fused);
hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
&fused);
if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
hw->phy.ops.read_reg(hw,
IGP01E1000_ANALOG_FUSE_STATUS,
&fused);
hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,
&fused);
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
@ -1194,19 +1172,19 @@ static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
} else if (coarse ==
IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
hw->phy.ops.write_reg(hw,
IGP01E1000_ANALOG_FUSE_CONTROL,
fused);
IGP01E1000_ANALOG_FUSE_CONTROL,
fused);
hw->phy.ops.write_reg(hw,
IGP01E1000_ANALOG_FUSE_BYPASS,
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
IGP01E1000_ANALOG_FUSE_BYPASS,
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
}
}

74
sys/dev/e1000/e1000_82541.h
View File

@ -37,55 +37,55 @@
#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
#define IGP01E1000_PHY_CHANNEL_NUM 4
#define IGP01E1000_PHY_CHANNEL_NUM 4
#define IGP01E1000_PHY_AGC_A 0x1172
#define IGP01E1000_PHY_AGC_B 0x1272
#define IGP01E1000_PHY_AGC_C 0x1472
#define IGP01E1000_PHY_AGC_D 0x1872
#define IGP01E1000_PHY_AGC_A 0x1172
#define IGP01E1000_PHY_AGC_B 0x1272
#define IGP01E1000_PHY_AGC_C 0x1472
#define IGP01E1000_PHY_AGC_D 0x1872
#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
#define IGP01E1000_PHY_DSP_RESET 0x1F33
#define IGP01E1000_PHY_DSP_RESET 0x1F33
#define IGP01E1000_PHY_DSP_FFE 0x1F35
#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
#define IGP01E1000_PHY_DSP_FFE 0x1F35
#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
#define IGP01E1000_IEEE_FORCE_GIG 0x0140
#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
#define IGP01E1000_IEEE_FORCE_GIG 0x0140
#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
#define IGP01E1000_AGC_LENGTH_SHIFT 7
#define IGP01E1000_AGC_RANGE 10
#define IGP01E1000_AGC_LENGTH_SHIFT 7
#define IGP01E1000_AGC_RANGE 10
#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
#define IGP01E1000_MSE_CHANNEL_D 0x000F
#define IGP01E1000_MSE_CHANNEL_C 0x00F0
#define IGP01E1000_MSE_CHANNEL_B 0x0F00
#define IGP01E1000_MSE_CHANNEL_A 0xF000
#define IGP01E1000_MSE_CHANNEL_D 0x000F
#define IGP01E1000_MSE_CHANNEL_C 0x00F0
#define IGP01E1000_MSE_CHANNEL_B 0x0F00
#define IGP01E1000_MSE_CHANNEL_A 0xF000
void e1000_init_script_state_82541(struct e1000_hw *hw, bool state);

38
sys/dev/e1000/e1000_82542.c
View File

@ -62,7 +62,7 @@ static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
DEBUGFUNC("e1000_init_phy_params_82542");
phy->type = e1000_phy_none;
phy->type = e1000_phy_none;
return ret_val;
}
@ -77,18 +77,18 @@ static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
DEBUGFUNC("e1000_init_nvm_params_82542");
nvm->address_bits = 6;
nvm->delay_usec = 50;
nvm->opcode_bits = 3;
nvm->type = e1000_nvm_eeprom_microwire;
nvm->word_size = 64;
nvm->address_bits = 6;
nvm->delay_usec = 50;
nvm->opcode_bits = 3;
nvm->type = e1000_nvm_eeprom_microwire;
nvm->word_size = 64;
/* Function Pointers */
nvm->ops.read = e1000_read_nvm_microwire;
nvm->ops.release = e1000_stop_nvm;
nvm->ops.write = e1000_write_nvm_microwire;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.read = e1000_read_nvm_microwire;
nvm->ops.release = e1000_stop_nvm;
nvm->ops.write = e1000_write_nvm_microwire;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
return E1000_SUCCESS;
}
@ -124,7 +124,8 @@ static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
/* link setup */
mac->ops.setup_link = e1000_setup_link_82542;
/* phy/fiber/serdes setup */
mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic;
mac->ops.setup_physical_interface =
e1000_setup_fiber_serdes_link_generic;
/* check for link */
mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
/* multicast address update */
@ -143,7 +144,8 @@ static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
/* clear hardware counters */
mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
/* link info */
mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic;
mac->ops.get_link_up_info =
e1000_get_speed_and_duplex_fiber_serdes_generic;
return E1000_SUCCESS;
}
@ -325,7 +327,7 @@ static s32 e1000_setup_link_82542(struct e1000_hw *hw)
hw->fc.requested_mode &= ~e1000_fc_tx_pause;
if (mac->report_tx_early == 1)
if (mac->report_tx_early)
hw->fc.requested_mode &= ~e1000_fc_rx_pause;
/*
@ -335,7 +337,7 @@ static s32 e1000_setup_link_82542(struct e1000_hw *hw)
hw->fc.current_mode = hw->fc.requested_mode;
DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
hw->fc.current_mode);
hw->fc.current_mode);
/* Call the necessary subroutine to configure the link. */
ret_val = mac->ops.setup_physical_interface(hw);
@ -419,9 +421,8 @@ static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
* HW expects these in little endian so we reverse the byte order
* from network order (big endian) to little endian
*/
rar_low = ((u32) addr[0] |
((u32) addr[1] << 8) |
((u32) addr[2] << 16) | ((u32) addr[3] << 24));
rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
((u32) addr[2] << 16) | ((u32) addr[3] << 24));
rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
@ -431,6 +432,7 @@ static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
return E1000_SUCCESS;
}

147
sys/dev/e1000/e1000_82543.c
View File

@ -47,9 +47,9 @@ static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
u16 *data);
u16 *data);
static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
u16 data);
u16 data);
static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
@ -62,7 +62,7 @@ static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
static s32 e1000_led_on_82543(struct e1000_hw *hw);
static s32 e1000_led_off_82543(struct e1000_hw *hw);
static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
u32 value);
u32 value);
static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
@ -71,7 +71,7 @@ static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
u16 count);
u16 count);
static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw);
@ -89,34 +89,34 @@ static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
DEBUGFUNC("e1000_init_phy_params_82543");
if (hw->phy.media_type != e1000_media_type_copper) {
phy->type = e1000_phy_none;
phy->type = e1000_phy_none;
goto out;
} else {
phy->ops.power_up = e1000_power_up_phy_copper;
phy->ops.power_down = e1000_power_down_phy_copper;
phy->ops.power_up = e1000_power_up_phy_copper;
phy->ops.power_down = e1000_power_down_phy_copper;
}
phy->addr = 1;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->reset_delay_us = 10000;
phy->type = e1000_phy_m88;
phy->addr = 1;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->reset_delay_us = 10000;
phy->type = e1000_phy_m88;
/* Function Pointers */
phy->ops.check_polarity = e1000_check_polarity_m88;
phy->ops.commit = e1000_phy_sw_reset_generic;
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
phy->ops.get_cable_length = e1000_get_cable_length_m88;
phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
phy->ops.read_reg = (hw->mac.type == e1000_82543)
? e1000_read_phy_reg_82543
: e1000_read_phy_reg_m88;
phy->ops.reset = (hw->mac.type == e1000_82543)
? e1000_phy_hw_reset_82543
: e1000_phy_hw_reset_generic;
phy->ops.write_reg = (hw->mac.type == e1000_82543)
? e1000_write_phy_reg_82543
: e1000_write_phy_reg_m88;
phy->ops.get_info = e1000_get_phy_info_m88;
phy->ops.check_polarity = e1000_check_polarity_m88;
phy->ops.commit = e1000_phy_sw_reset_generic;
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
phy->ops.get_cable_length = e1000_get_cable_length_m88;
phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
phy->ops.read_reg = (hw->mac.type == e1000_82543)
? e1000_read_phy_reg_82543
: e1000_read_phy_reg_m88;
phy->ops.reset = (hw->mac.type == e1000_82543)
? e1000_phy_hw_reset_82543
: e1000_phy_hw_reset_generic;
phy->ops.write_reg = (hw->mac.type == e1000_82543)
? e1000_write_phy_reg_82543
: e1000_write_phy_reg_m88;
phy->ops.get_info = e1000_get_phy_info_m88;
/*
* The external PHY of the 82543 can be in a funky state.
@ -170,18 +170,18 @@ static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
DEBUGFUNC("e1000_init_nvm_params_82543");
nvm->type = e1000_nvm_eeprom_microwire;
nvm->word_size = 64;
nvm->delay_usec = 50;
nvm->address_bits = 6;
nvm->opcode_bits = 3;
nvm->type = e1000_nvm_eeprom_microwire;
nvm->word_size = 64;
nvm->delay_usec = 50;
nvm->address_bits = 6;
nvm->opcode_bits = 3;
/* Function Pointers */
nvm->ops.read = e1000_read_nvm_microwire;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.read = e1000_read_nvm_microwire;
nvm->ops.update = e1000_update_nvm_checksum_generic;
nvm->ops.valid_led_default = e1000_valid_led_default_generic;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.write = e1000_write_nvm_microwire;
nvm->ops.validate = e1000_validate_nvm_checksum_generic;
nvm->ops.write = e1000_write_nvm_microwire;
return E1000_SUCCESS;
}
@ -226,19 +226,18 @@ static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
mac->ops.setup_link = e1000_setup_link_82543;
/* physical interface setup */
mac->ops.setup_physical_interface =
(hw->phy.media_type == e1000_media_type_copper)
? e1000_setup_copper_link_82543
: e1000_setup_fiber_link_82543;
(hw->phy.media_type == e1000_media_type_copper)
? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543;
/* check for link */
mac->ops.check_for_link =
(hw->phy.media_type == e1000_media_type_copper)
? e1000_check_for_copper_link_82543
: e1000_check_for_fiber_link_82543;
(hw->phy.media_type == e1000_media_type_copper)
? e1000_check_for_copper_link_82543
: e1000_check_for_fiber_link_82543;
/* link info */
mac->ops.get_link_up_info =
(hw->phy.media_type == e1000_media_type_copper)
? e1000_get_speed_and_duplex_copper_generic
: e1000_get_speed_and_duplex_fiber_serdes_generic;
(hw->phy.media_type == e1000_media_type_copper)
? e1000_get_speed_and_duplex_copper_generic
: e1000_get_speed_and_duplex_fiber_serdes_generic;
/* multicast address update */
mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
/* writing VFTA */
@ -295,8 +294,7 @@ static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
goto out;
}
state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED)
? TRUE : FALSE;
state = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED);
out:
return state;
@ -348,8 +346,7 @@ bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
goto out;
}
state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED)
? TRUE : FALSE;
state = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED);
out:
return state;
@ -412,8 +409,8 @@ out:
* Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
**/
void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
struct e1000_hw_stats *stats, u32 frame_len,
u8 *mac_addr, u32 max_frame_size)
struct e1000_hw_stats *stats, u32 frame_len,
u8 *mac_addr, u32 max_frame_size)
{
if (!(e1000_tbi_sbp_enabled_82543(hw)))
goto out;
@ -425,12 +422,12 @@ void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
* counters overcount this packet as a CRC error and undercount
* the packet as a good packet
*/
/* This packet should not be counted as a CRC error. */
/* This packet should not be counted as a CRC error. */
stats->crcerrs--;
/* This packet does count as a Good Packet Received. */
/* This packet does count as a Good Packet Received. */
stats->gprc++;
/* Adjust the Good Octets received counters */
/* Adjust the Good Octets received counters */
stats->gorc += frame_len;
/*
@ -446,7 +443,7 @@ void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
stats->mprc++;
/*
* In this case, the hardware has overcounted the number of
* In this case, the hardware has over counted the number of
* oversize frames.
*/
if ((frame_len == max_frame_size) && (stats->roc > 0))
@ -513,7 +510,7 @@ static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
* e1000_shift_out_mdi_bits routine five different times. The format
* of an MII read instruction consists of a shift out of 14 bits and
* is defined as follows:
* <Preamble><SOF><Op Code><Phy Addr><Offset>
* <Preamble><SOF><Op Code><Phy Addr><Offset>
* followed by a shift in of 18 bits. This first two bits shifted in
* are TurnAround bits used to avoid contention on the MDIO pin when a
* READ operation is performed. These two bits are thrown away
@ -572,9 +569,9 @@ static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
mdic <<= 16;
mdic |= (u32) data;
mdic |= (u32)data;
e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
@ -631,7 +628,7 @@ static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
* In order to do this, "data" must be broken down into bits.
**/
static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
u16 count)
u16 count)
{
u32 ctrl, mask;
@ -642,7 +639,7 @@ static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
* into bits.
*/
mask = 0x01;
mask <<= (count -1);
mask <<= (count - 1);
ctrl = E1000_READ_REG(hw, E1000_CTRL);
@ -656,8 +653,10 @@ static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
* A "0" is shifted out to the PHY by setting the MDIO bit to
* "0" and then raising and lowering the clock.
*/
if (data & mask) ctrl |= E1000_CTRL_MDIO;
else ctrl &= ~E1000_CTRL_MDIO;
if (data & mask)
ctrl |= E1000_CTRL_MDIO;
else
ctrl &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
@ -749,8 +748,8 @@ static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
if (ret_val)
goto out;
if (!hw->mac.autoneg &&
(hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex &
E1000_ALL_10_SPEED))
ret_val = e1000_polarity_reversal_workaround_82543(hw);
out:
@ -808,7 +807,7 @@ static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
if (ret_val)
goto out;
if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
if (!(mii_status_reg & ~MII_SR_LINK_STATUS))
break;
msec_delay_irq(100);
}
@ -1040,7 +1039,7 @@ static s32 e1000_setup_link_82543(struct e1000_hw *hw)
goto out;
}
ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
NVM_SWDPIO_EXT_SHIFT);
NVM_SWDPIO_EXT_SHIFT);
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
}
@ -1114,10 +1113,8 @@ static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
ret_val = e1000_phy_has_link_generic(hw,
COPPER_LINK_UP_LIMIT,
10,
&link);
ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
&link);
if (ret_val)
goto out;
@ -1177,11 +1174,10 @@ static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
* optics detect a signal. If we have a signal, then poll for a
* "Link-Up" indication.
*/
if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1))
ret_val = e1000_poll_fiber_serdes_link_generic(hw);
} else {
else
DEBUGOUT("No signal detected\n");
}
out:
return ret_val;
@ -1275,9 +1271,8 @@ static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
* different link partner.
*/
ret_val = e1000_config_fc_after_link_up_generic(hw);
if (ret_val) {
if (ret_val)
DEBUGOUT("Error configuring flow control\n");
}
/*
* At this point we know that we are on copper and we have
@ -1359,8 +1354,8 @@ static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
(!(status & E1000_STATUS_LU)) &&
(!(rxcw & E1000_RXCW_C))) {
if (mac->autoneg_failed == 0) {
mac->autoneg_failed = 1;
if (!mac->autoneg_failed) {
mac->autoneg_failed = TRUE;
ret_val = 0;
goto out;
}

26
sys/dev/e1000/e1000_82543.h
View File

@ -35,23 +35,23 @@
#ifndef _E1000_82543_H_
#define _E1000_82543_H_
#define PHY_PREAMBLE 0xFFFFFFFF
#define PHY_PREAMBLE_SIZE 32
#define PHY_SOF 0x1
#define PHY_OP_READ 0x2
#define PHY_OP_WRITE 0x1
#define PHY_TURNAROUND 0x2
#define PHY_PREAMBLE 0xFFFFFFFF
#define PHY_PREAMBLE_SIZE 32
#define PHY_SOF 0x1
#define PHY_OP_READ 0x2
#define PHY_OP_WRITE 0x1
#define PHY_TURNAROUND 0x2
#define TBI_COMPAT_ENABLED 0x1 /* Global "knob" for the workaround */
#define TBI_COMPAT_ENABLED 0x1 /* Global "knob" for the workaround */
/* If TBI_COMPAT_ENABLED, then this is the current state (on/off) */
#define TBI_SBP_ENABLED 0x2
#define TBI_SBP_ENABLED 0x2
void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
struct e1000_hw_stats *stats,
u32 frame_len, u8 *mac_addr,
u32 max_frame_size);
struct e1000_hw_stats *stats,
u32 frame_len, u8 *mac_addr,
u32 max_frame_size);
void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw,
bool state);
bool state);
bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw);
#endif

28
sys/dev/e1000/e1000_82571.h
View File

@ -35,29 +35,29 @@
#ifndef _E1000_82571_H_
#define _E1000_82571_H_
#define ID_LED_RESERVED_F746 0xF746
#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
(ID_LED_OFF1_ON2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \
(ID_LED_DEF1_DEF2))
#define ID_LED_RESERVED_F746 0xF746
#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
(ID_LED_OFF1_ON2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \
(ID_LED_DEF1_DEF2))
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
/* Intr Throttling - RW */
#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
#define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
#define E1000_EIAC_MASK_82574 0x01F00000
#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
#define E1000_EIAC_MASK_82574 0x01F00000
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
#define E1000_RXCFGL 0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
#define E1000_BASE1000T_STATUS 10
#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
#define E1000_RECEIVE_ERROR_COUNTER 21
#define E1000_RECEIVE_ERROR_MAX 0xFFFF
#define E1000_BASE1000T_STATUS 10
#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
#define E1000_RECEIVE_ERROR_COUNTER 21
#define E1000_RECEIVE_ERROR_MAX 0xFFFF
bool e1000_check_phy_82574(struct e1000_hw *hw);
bool e1000_get_laa_state_82571(struct e1000_hw *hw);
void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state);

4
sys/dev/e1000/e1000_82575.c
View File

@ -1051,7 +1051,7 @@ static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
u32 swmask = mask;
u32 fwmask = mask << 16;
s32 ret_val = E1000_SUCCESS;
s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
s32 i = 0, timeout = 200;
DEBUGFUNC("e1000_acquire_swfw_sync_82575");
@ -2126,7 +2126,7 @@ static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
* e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
* @hw: pointer to the HW structure
*
* After rx enable if managability is enabled then there is likely some
* After Rx enable, if manageability is enabled then there is likely some
* bad data at the start of the fifo and possibly in the DMA fifo. This
* function clears the fifos and flushes any packets that came in as rx was
* being enabled.

16
sys/dev/e1000/e1000_api.h
View File

@ -124,14 +124,14 @@ u32 e1000_translate_register_82542(u32 reg);
* TBI_ACCEPT macro definition:
*
* This macro requires:
* adapter = a pointer to struct e1000_hw
* a = a pointer to struct e1000_hw
* status = the 8 bit status field of the Rx descriptor with EOP set
* error = the 8 bit error field of the Rx descriptor with EOP set
* errors = the 8 bit error field of the Rx descriptor with EOP set
* length = the sum of all the length fields of the Rx descriptors that
* make up the current frame
* last_byte = the last byte of the frame DMAed by the hardware
* max_frame_length = the maximum frame length we want to accept.
* min_frame_length = the minimum frame length we want to accept.
* min_frame_size = the minimum frame length we want to accept.
* max_frame_size = the maximum frame length we want to accept.
*
* This macro is a conditional that should be used in the interrupt
* handler's Rx processing routine when RxErrors have been detected.
@ -157,10 +157,10 @@ u32 e1000_translate_register_82542(u32 reg);
(((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
((last_byte) == CARRIER_EXTENSION) && \
(((status) & E1000_RXD_STAT_VP) ? \
(((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
((length) <= (max_frame_size + 1))) : \
(((length) > min_frame_size) && \
((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
(((length) > ((min_frame_size) - VLAN_TAG_SIZE)) && \
((length) <= ((max_frame_size) + 1))) : \
(((length) > (min_frame_size)) && \
((length) <= ((max_frame_size) + VLAN_TAG_SIZE + 1)))))
#define E1000_MAX(a, b) ((a) > (b) ? (a) : (b))
#define E1000_DIVIDE_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) /* ceil(a/b) */

2
sys/dev/e1000/e1000_hw.h
View File

@ -787,7 +787,7 @@ struct e1000_mac_info {
u16 uta_reg_count;
/* Maximum size of the MTA register table in all supported adapters */
#define MAX_MTA_REG 128
#define MAX_MTA_REG 128
u32 mta_shadow[MAX_MTA_REG];
u16 rar_entry_count;

6
sys/dev/e1000/e1000_ich8lan.c
View File

@ -1087,7 +1087,7 @@ static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
u16 speed, duplex, scale = 0;
u16 max_snoop, max_nosnoop;
u16 max_ltr_enc; /* max LTR latency encoded */
s64 lat_ns; /* latency (ns) */
s64 lat_ns;
s64 value;
u32 rxa;
@ -1119,8 +1119,8 @@ static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
lat_ns = 0;
else
lat_ns /= speed;
value = lat_ns;
while (value > E1000_LTRV_VALUE_MASK) {
scale++;
value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
@ -2997,7 +2997,6 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
u16 oem_reg;
DEBUGFUNC("e1000_set_lplu_state_pchlan");
ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
if (ret_val)
return ret_val;
@ -4998,7 +4997,6 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
s32 ret_val;
DEBUGFUNC("e1000_resume_workarounds_pchlan");
if (hw->mac.type < e1000_pch2lan)
return;

1
sys/dev/e1000/e1000_manage.c
View File

@ -33,7 +33,6 @@
/*$FreeBSD$*/
#include "e1000_api.h"
/**
* e1000_calculate_checksum - Calculate checksum for buffer
* @buffer: pointer to EEPROM

11
sys/dev/e1000/e1000_phy.c
View File

@ -3122,7 +3122,7 @@ s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
/* Page 800 works differently than the rest so it has its own func */
if (page == BM_WUC_PAGE) {
ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
FALSE, FALSE);
FALSE, false);
goto release;
}
@ -3286,7 +3286,7 @@ s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
/* Page 800 works differently than the rest so it has its own func */
if (page == BM_WUC_PAGE) {
ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
FALSE, FALSE);
FALSE, false);
goto release;
}
@ -3433,6 +3433,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
u16 phy_reg = 0;
DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
reg = BM_PHY_REG_NUM(offset);
page = BM_PHY_REG_PAGE(offset);
@ -3544,7 +3545,6 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
if (ret_val)
return ret_val;
}
/* Page 800 works differently than the rest so it has its own func */
if (page == BM_WUC_PAGE) {
ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
@ -3598,7 +3598,7 @@ out:
**/
s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
{
return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE);
return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false);
}
/**
@ -3654,7 +3654,6 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
if (ret_val)
return ret_val;
}
/* Page 800 works differently than the rest so it has its own func */
if (page == BM_WUC_PAGE) {
ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
@ -3724,7 +3723,7 @@ out:
**/
s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
{
return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE);
return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false);
}
/**

4
sys/dev/e1000/e1000_regs.h
View File

@ -202,7 +202,7 @@
/* Queues fetch arbitration priority control register */
#define E1000_I210_TQAVARBCTRL 0x3574
/* Queues priority masks where _n and _p can be 0-3. */
#define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * _n))
#define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n)))
/* QAV Tx mode control registers where _n can be 0 or 1. */
#define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n))
@ -215,7 +215,7 @@
#define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))
/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
#define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n))
#define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n)))
#define E1000_MMDAC 13 /* MMD Access Control */
#define E1000_MMDAAD 14 /* MMD Access Address/Data */