cxgbe(4): Update T4 and T5 firmwares to 1.9.12.0
This commit is contained in:
Navdeep Parhar
parent
e3ededfa24
commit
48d05478bf
@ -1199,7 +1199,7 @@ t4fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t4fw.fwo"
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t4fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.8.11.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.9.12.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t4fw.fw"
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@ -1223,7 +1223,7 @@ t5fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t5fw.fwo"
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t5fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.8.22.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.9.12.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t5fw.fw"
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@ -246,7 +246,7 @@ struct pci_params {
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* Firmware device log.
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*/
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struct devlog_params {
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u32 memtype; /* which memory (EDC0, EDC1, MC) */
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u32 memtype; /* which memory (FW_MEMTYPE_* ) */
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u32 start; /* start of log in firmware memory */
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u32 size; /* size of log */
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};
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File diff suppressed because it is too large
Load Diff
8705
sys/dev/cxgbe/firmware/t4fw-1.9.12.0.bin.uu
Normal file
8705
sys/dev/cxgbe/firmware/t4fw-1.9.12.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -14,10 +14,14 @@
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sge_timer_value = 1, 5, 10, 50, 100, 200 # usecs
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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# TP_SHIFT_CNT
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reg[0x7dc0] = 0x62f8849
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filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
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filterMask = protocol, fcoe
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# TP rx and tx channels (0 = auto).
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tp_nrxch = 0
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@ -29,6 +33,9 @@
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tp_pmrx_pagesize = 64K
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tp_pmtx_pagesize = 64K
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# TP OFLD MTUs
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tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
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# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
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# these 4 PFs only. Not used here at all.
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[function "0"]
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@ -141,7 +148,7 @@
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[fini]
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version = 0x1
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checksum = 0x6cc2514b
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checksum = 0x6f516705
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#
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# $FreeBSD$
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#
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@ -1,6 +1,6 @@
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# Chelsio T4 Factory Default configuration file.
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#
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# Copyright (C) 2010-2012 Chelsio Communications. All rights reserved.
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# Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
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#
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# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
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# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
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@ -109,17 +109,23 @@
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reg[0x10a8] = 0x2000/0x2000 # SGE_DOORBELL_CONTROL
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sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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reg[0x7dc0] = 0x62f8849 # TP_SHIFT_CNT
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# Selection of tuples for LE filter lookup, fields (and widths which
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# must sum to <= 36): { IP Fragment (1), MPS Match Type (3),
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# IP Protocol (8), [Inner] VLAN (17), Port (3), FCoE (1) }
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#
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# TP_VLAN_PRI_MAP to select filter tuples
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# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
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# protocol, tos, vlan, vnic_id, port, fcoe
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# valid filterModes are described the Terminator 4 Data Book
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filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
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# filter tuples enforced in LE active region (equal to or subset of filterMode)
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filterMask = protocol, fcoe
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP RX payload
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tp_pmrx = 30
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tp_pmrx = 34
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# TP RX payload page size
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tp_pmrx_pagesize = 64K
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@ -129,7 +135,7 @@
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP TX payload
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tp_pmtx = 50
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tp_pmtx = 32
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# TP TX payload page size
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tp_pmtx_pagesize = 64K
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@ -137,6 +143,9 @@
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# TP number of TX channels
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tp_ntxch = 0 # 0 (auto) = equal number of ports
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# TP OFLD MTUs
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tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
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# Some "definitions" to make the rest of this a bit more readable. We support
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# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
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# per function per port ...
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@ -361,11 +370,11 @@
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nhash = 12288 # number of hash region entries
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protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu
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tp_l2t = 3072
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tp_ddp = 2
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tp_ddp = 3
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tp_ddp_iscsi = 2
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tp_stag = 2
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tp_pbl = 5
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tp_rq = 7
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tp_stag = 3
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tp_pbl = 10
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tp_rq = 13
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# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
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# need to have Virtual Interfaces on each of the four ports with up to NCPUS
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@ -405,7 +414,7 @@
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pmask = all # access to all four ports ...
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nhash = 2048
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protocol = fcoe_initiator
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tp_ddp = 2
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tp_ddp = 1
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fcoe_nfcf = 16
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fcoe_nvnp = 32
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fcoe_nssn = 1024
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@ -520,8 +529,8 @@
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dwm = 30
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[fini]
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version = 0x1425000d
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checksum = 0x25c2f782
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version = 0x14250010
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checksum = 0x5a5526c3
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# Total resources used by above allocations:
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# Virtual Interfaces: 104
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@ -75,6 +75,19 @@ enum fw_retval {
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FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
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};
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/******************************************************************************
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* M E M O R Y T Y P E s
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******************************/
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enum fw_memtype {
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FW_MEMTYPE_EDC0 = 0x0,
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FW_MEMTYPE_EDC1 = 0x1,
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FW_MEMTYPE_EXTMEM = 0x2,
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FW_MEMTYPE_FLASH = 0x4,
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FW_MEMTYPE_INTERNAL = 0x5,
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FW_MEMTYPE_EXTMEM1 = 0x6,
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};
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/******************************************************************************
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* W O R K R E Q U E S T s
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********************************/
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@ -85,6 +98,7 @@ enum fw_wr_opcodes {
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FW_ULPTX_WR = 0x04,
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FW_TP_WR = 0x05,
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FW_ETH_TX_PKT_WR = 0x08,
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FW_ETH_TX_PKT2_WR = 0x44,
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FW_ETH_TX_PKTS_WR = 0x09,
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FW_ETH_TX_UO_WR = 0x1c,
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FW_EQ_FLUSH_WR = 0x1b,
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@ -566,6 +580,64 @@ struct fw_eth_tx_pkt_wr {
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#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
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(((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
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struct fw_eth_tx_pkt2_wr {
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__be32 op_immdlen;
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__be32 equiq_to_len16;
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__be32 r3;
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__be32 L4ChkDisable_to_IpHdrLen;
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};
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#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0
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#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff
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#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
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#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \
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(((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
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#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31
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#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1
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#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
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((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
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#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
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(((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
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M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
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#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \
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V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
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#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30
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#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1
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#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
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((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
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#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
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(((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
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M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
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#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \
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V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
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#define S_FW_ETH_TX_PKT2_WR_IVLAN 28
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#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1
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#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
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#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \
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(((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
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#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
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#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12
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#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff
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#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
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#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \
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(((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
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#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8
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#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf
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#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
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#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \
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(((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
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#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0
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#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff
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#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
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#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \
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(((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
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struct fw_eth_tx_pkts_wr {
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__be32 op_pkd;
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__be32 equiq_to_len16;
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@ -773,9 +845,36 @@ struct fw_ofld_tx_data_wr {
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__be32 op_to_immdlen;
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__be32 flowid_len16;
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__be32 plen;
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__be32 tunnel_to_proxy;
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__be32 lsodisable_to_proxy;
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};
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#define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31
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#define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1
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#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
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((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
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#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
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(((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
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M_FW_OFLD_TX_DATA_WR_LSODISABLE)
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#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
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#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30
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#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1
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#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
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((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
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#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
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(((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
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#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
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#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29
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#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1
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#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
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((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
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#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
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(((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
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M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
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#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \
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V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
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#define S_FW_OFLD_TX_DATA_WR_TUNNEL 19
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#define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1
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#define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL)
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@ -3396,6 +3495,8 @@ enum fw_caps_config_nic {
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FW_CAPS_CONFIG_NIC_IDS = 0x00000004,
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FW_CAPS_CONFIG_NIC_UM = 0x00000008,
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FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010,
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FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
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FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
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};
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enum fw_caps_config_toe {
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@ -3424,15 +3525,6 @@ enum fw_caps_config_fcoe {
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FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
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};
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enum fw_memtype_cf {
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FW_MEMTYPE_CF_EDC0 = 0x0,
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FW_MEMTYPE_CF_EDC1 = 0x1,
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FW_MEMTYPE_CF_EXTMEM = 0x2,
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FW_MEMTYPE_CF_FLASH = 0x4,
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FW_MEMTYPE_CF_INTERNAL = 0x5,
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FW_MEMTYPE_CF_EXTMEM1 = 0x6,
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};
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struct fw_caps_config_cmd {
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__be32 op_to_write;
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__be32 cfvalid_to_len16;
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@ -5924,6 +6016,7 @@ enum fw_port_mod_sub_type {
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FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
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FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
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FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
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FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
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FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
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/*
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@ -7627,13 +7720,13 @@ enum fw_hdr_chip {
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enum {
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T4FW_VERSION_MAJOR = 0x01,
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T4FW_VERSION_MINOR = 0x08,
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T4FW_VERSION_MICRO = 0x0b,
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T4FW_VERSION_MINOR = 0x09,
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T4FW_VERSION_MICRO = 0x0c,
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T4FW_VERSION_BUILD = 0x00,
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T5FW_VERSION_MAJOR = 0x01,
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T5FW_VERSION_MINOR = 0x08,
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T5FW_VERSION_MICRO = 0x16,
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T5FW_VERSION_MINOR = 0x09,
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T5FW_VERSION_MICRO = 0x0c,
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T5FW_VERSION_BUILD = 0x00,
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};
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File diff suppressed because it is too large
Load Diff
8417
sys/dev/cxgbe/firmware/t5fw-1.9.12.0.bin.uu
Normal file
8417
sys/dev/cxgbe/firmware/t5fw-1.9.12.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -17,12 +17,18 @@
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sge_timer_value = 1, 5, 10, 50, 100, 200 # usecs
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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# TP_SHIFT_CNT
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reg[0x7dc0] = 0x62f8849
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# TP_GLOBAL_CONFIG
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reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
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# TP_PARA_REG0
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reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
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filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
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filterMask = protocol, fcoe
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||||
|
||||
@ -36,6 +42,13 @@
|
||||
tp_pmrx_pagesize = 64K
|
||||
tp_pmtx_pagesize = 64K
|
||||
|
||||
# TP OFLD MTUs
|
||||
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
|
||||
|
||||
# MC configuration
|
||||
mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
|
||||
mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC
|
||||
|
||||
# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
|
||||
# these 4 PFs only. Not used here at all.
|
||||
[function "0"]
|
||||
@ -148,7 +161,7 @@
|
||||
|
||||
[fini]
|
||||
version = 0x1
|
||||
checksum = 0x93f11b53
|
||||
checksum = 0x9f27febc
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
@ -135,13 +135,20 @@
|
||||
# function of number of egress queues
|
||||
# used
|
||||
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE
|
||||
reg[0x7d04] = 0x00010000/0x00010000
|
||||
|
||||
reg[0x7dc0] = 0x062f8849 # TP_SHIFT_CNT
|
||||
|
||||
# Selection of tuples for LE filter lookup, fields (and widths which
|
||||
# must sum to <= 36): { IP Fragment (1), MPS Match Type (3),
|
||||
# IP Protocol (8), [Inner] VLAN (17), Port (3), FCoE (1) }
|
||||
#
|
||||
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
|
||||
# filter control: compact, fcoemask
|
||||
# server sram : srvrsram
|
||||
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
|
||||
# protocol, tos, vlan, vnic_id, port, fcoe
|
||||
# valid filterModes are described the Terminator 5 Data Book
|
||||
filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
|
||||
|
||||
# filter tuples enforced in LE active region (equal to or subset of filterMode)
|
||||
filterMask = protocol, fcoe
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
@ -164,12 +171,22 @@
|
||||
# TP number of TX channels
|
||||
tp_ntxch = 0 # 0 (auto) = equal number of ports
|
||||
|
||||
# TP OFLD MTUs
|
||||
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
|
||||
|
||||
# TP_GLOBAL_CONFIG
|
||||
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
|
||||
|
||||
# TP_PARA_REG0
|
||||
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
|
||||
|
||||
# LE_DB_CONFIG
|
||||
reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable
|
||||
|
||||
# MC configuration
|
||||
mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
|
||||
mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
|
||||
# per function per port ...
|
||||
@ -553,8 +570,8 @@
|
||||
dwm = 30
|
||||
|
||||
[fini]
|
||||
version = 0x1425000f
|
||||
checksum = 0x23a2d850
|
||||
version = 0x14250013
|
||||
checksum = 0xd66f5b23
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
|
||||
@ -332,6 +332,7 @@ static int map_bars_0_and_4(struct adapter *);
|
||||
static int map_bar_2(struct adapter *);
|
||||
static void setup_memwin(struct adapter *);
|
||||
static int validate_mem_range(struct adapter *, uint32_t, int);
|
||||
static int fwmtype_to_hwmtype(int);
|
||||
static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
|
||||
uint32_t *);
|
||||
static void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
|
||||
@ -1576,6 +1577,24 @@ validate_mem_range(struct adapter *sc, uint32_t addr, int len)
|
||||
return (EFAULT);
|
||||
}
|
||||
|
||||
static int
|
||||
fwmtype_to_hwmtype(int mtype)
|
||||
{
|
||||
|
||||
switch (mtype) {
|
||||
case FW_MEMTYPE_EDC0:
|
||||
return (MEM_EDC0);
|
||||
case FW_MEMTYPE_EDC1:
|
||||
return (MEM_EDC1);
|
||||
case FW_MEMTYPE_EXTMEM:
|
||||
return (MEM_MC0);
|
||||
case FW_MEMTYPE_EXTMEM1:
|
||||
return (MEM_MC1);
|
||||
default:
|
||||
panic("%s: cannot translate fw mtype %d.", __func__, mtype);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Verify that the memory range specified by the memtype/offset/len pair is
|
||||
* valid and lies entirely within the memtype specified. The global address of
|
||||
@ -1592,7 +1611,7 @@ validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
|
||||
return (EINVAL);
|
||||
|
||||
em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
|
||||
switch (mtype) {
|
||||
switch (fwmtype_to_hwmtype(mtype)) {
|
||||
case MEM_EDC0:
|
||||
if (!(em & F_EDRAM0_ENABLE))
|
||||
return (EINVAL);
|
||||
@ -2293,7 +2312,7 @@ partition_resources(struct adapter *sc, const struct firmware *default_cfg,
|
||||
}
|
||||
} else {
|
||||
use_config_on_flash:
|
||||
mtype = FW_MEMTYPE_CF_FLASH;
|
||||
mtype = FW_MEMTYPE_FLASH;
|
||||
moff = t4_flash_cfg_addr(sc);
|
||||
}
|
||||
|
||||
@ -5306,12 +5325,12 @@ sysctl_devlog(SYSCTL_HANDLER_ARGS)
|
||||
struct adapter *sc = arg1;
|
||||
struct devlog_params *dparams = &sc->params.devlog;
|
||||
struct fw_devlog_e *buf, *e;
|
||||
int i, j, rc, nentries, first = 0;
|
||||
int i, j, rc, nentries, first = 0, m;
|
||||
struct sbuf *sb;
|
||||
uint64_t ftstamp = UINT64_MAX;
|
||||
|
||||
if (dparams->start == 0) {
|
||||
dparams->memtype = 0;
|
||||
dparams->memtype = FW_MEMTYPE_EDC0;
|
||||
dparams->start = 0x84000;
|
||||
dparams->size = 32768;
|
||||
}
|
||||
@ -5322,8 +5341,8 @@ sysctl_devlog(SYSCTL_HANDLER_ARGS)
|
||||
if (buf == NULL)
|
||||
return (ENOMEM);
|
||||
|
||||
rc = -t4_mem_read(sc, dparams->memtype, dparams->start, dparams->size,
|
||||
(void *)buf);
|
||||
m = fwmtype_to_hwmtype(dparams->memtype);
|
||||
rc = -t4_mem_read(sc, m, dparams->start, dparams->size, (void *)buf);
|
||||
if (rc != 0)
|
||||
goto done;
|
||||
|
||||
|
||||
@ -452,7 +452,7 @@ write_tx_wr(void *dst, struct toepcb *toep, unsigned int immdlen,
|
||||
V_FW_WR_IMMDLEN(immdlen));
|
||||
txwr->flowid_len16 = htobe32(V_FW_WR_FLOWID(toep->tid) |
|
||||
V_FW_WR_LEN16(credits));
|
||||
txwr->tunnel_to_proxy =
|
||||
txwr->lsodisable_to_proxy =
|
||||
htobe32(V_FW_OFLD_TX_DATA_WR_ULPMODE(toep->ulp_mode) |
|
||||
V_FW_OFLD_TX_DATA_WR_URGENT(0) | /* XXX */
|
||||
V_FW_OFLD_TX_DATA_WR_SHOVE(shove));
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS += ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T4FW_VER = 1.8.11.0
|
||||
T4FW_VER = 1.9.12.0
|
||||
FIRMWS += t4fw.fw:t4fw:${T4FW_VER}
|
||||
CLEANFILES += t4fw.fw
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS += ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T5FW_VER = 1.8.22.0
|
||||
T5FW_VER = 1.9.12.0
|
||||
FIRMWS += t5fw.fw:t5fw:${T5FW_VER}
|
||||
CLEANFILES += t5fw.fw
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user