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Older Book-E processors (e500v1/e500v2) don't support dcbzl.

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The only difference between dcbzl and dcbz is dcbzl operates on native cache
line lengths regardless of L1CSR0[DCBZ32].  Since we don't change the cache line
size, the cacheline_size variable will reflect the used cache line length, and
dcbz will work as expected.
This commit is contained in:
Justin Hibbits 2016-01-26 04:41:18 +00:00
parent 30857edaea
commit 49d36ba409
1 changed files with 1 additions and 1 deletions
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2
sys/powerpc/booke/pmap.c
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@ -2254,7 +2254,7 @@ mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
for (off = 0; off < PAGE_SIZE; off += cacheline_size)
__asm __volatile("dcbzl 0,%0" :: "r"(va + off));
__asm __volatile("dcbz 0,%0" :: "r"(va + off));
mmu_booke_kremove(mmu, va);
mtx_unlock(&zero_page_mutex);