Wait for DesignWare UART transfers completion before accessing line control
When using DW UART with BUSY detection it is necessary to wait until all serial transfers are finished before manipulating the line control. LCR will not be affected when UART is busy. In addition, if Divisor Latch Access Bit is being set in order to modify UART divisors: 1. We will get BUSY interrupt if interrupts are enabled. 2. Because LCR will not be affected the THR and (even worse) IER contents will be corrupted. This will lead to console hang. Approved by: cognet (mentor)
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@ -185,6 +185,7 @@
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#define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */
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#define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */
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#define REG_USR com_usr
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#define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */
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#define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */
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/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */
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@ -647,11 +647,35 @@ int
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ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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struct ns8250_softc *ns8250;
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struct uart_bas *bas;
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int error;
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int error, limit;
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ns8250 = (struct ns8250_softc*)sc;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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/*
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* When using DW UART with BUSY detection it is necessary to wait
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* until all serial transfers are finished before manipulating the
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* line control. LCR will not be affected when UART is busy.
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*/
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if (ns8250->busy_detect != 0) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop in case when the hardware is broken.
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*/
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limit = 10 * 1024;
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while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
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--limit)
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DELAY(4);
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if (limit <= 0) {
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/* UART appears to be stuck */
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uart_unlock(sc->sc_hwmtx);
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return (EIO);
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}
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}
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error = ns8250_param(bas, baudrate, databits, stopbits, parity);
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uart_unlock(sc->sc_hwmtx);
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return (error);
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