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Add a new option to limit the maximum size of aggregates.

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The default is to limit them to what the hardware is capable of.

Add sysctl twiddles for both the non-RTS and RTS protected aggregate
generation.

Whilst here, add some comments about stuff that I've discovered during
my exploration of the TX aggregate / delimiter setup path from the
reference driver.
This commit is contained in:
Adrian Chadd 2013-02-21 06:18:40 +00:00
parent 054eace83f
commit 4a502c332a
5 changed files with 32 additions and 2 deletions
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1
sys/dev/ath/if_ath.c
View File

@ -799,6 +799,7 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH;
sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
/*
* Check if the hardware requires PCI register serialisation.

8
sys/dev/ath/if_ath_sysctl.c
View File

@ -704,7 +704,7 @@ ath_sysctlattach(struct ath_softc *sc)
SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"hwq_limit", CTLFLAG_RW, &sc->sc_hwq_limit, 0,
"");
"Hardware queue depth before software-queuing TX frames");
SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"tid_hwq_lo", CTLFLAG_RW, &sc->sc_tid_hwq_lo, 0,
"");
@ -712,6 +712,12 @@ ath_sysctlattach(struct ath_softc *sc)
"tid_hwq_hi", CTLFLAG_RW, &sc->sc_tid_hwq_hi, 0,
"");
/* Aggregate length twiddles */
SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"aggr_limit", CTLFLAG_RW, &sc->sc_aggr_limit, 0, "");
SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"rts_aggr_limit", CTLFLAG_RW, &sc->sc_rts_aggr_limit, 0, "");
SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"txq_data_minfree", CTLFLAG_RW, &sc->sc_txq_data_minfree,
0, "Minimum free buffers before adding a data frame"

5
sys/dev/ath/if_ath_tx.h
View File

@ -79,6 +79,11 @@
#define BAW_WITHIN(_start, _bawsz, _seqno) \
((((_seqno) - (_start)) & 4095) < (_bawsz))
/*
* Maximum aggregate size
*/
#define ATH_AGGR_MAXSIZE 65530
extern void ath_freetx(struct mbuf *m);
extern void ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an);
extern void ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq);

19
sys/dev/ath/if_ath_tx_ht.c
View File

@ -346,12 +346,19 @@ ath_compute_num_delims(struct ath_softc *sc, struct ath_buf *first_bf,
* crypto hardware catch up. This could be tuned per-MAC and
* per-rate, but for now we'll simply assume encryption is
* always enabled.
*
* Also note that the Atheros reference driver inserts two
* delimiters by default for pre-AR9380 peers. This will
* include "that" required delimiter.
*/
ndelim += ATH_AGGR_ENCRYPTDELIM;
/*
* For AR9380, there's a minimum number of delimeters
* required when doing RTS.
*
* XXX TODO: this is only needed if (a) RTS/CTS is enabled, and
* XXX (b) this is the first sub-frame in the aggregate.
*/
if (sc->sc_use_ent && (sc->sc_ent_cfg & AH_ENT_RTSCTS_DELIM_WAR)
&& ndelim < AH_FIRST_DESC_NDELIMS)
@ -420,9 +427,12 @@ ath_compute_num_delims(struct ath_softc *sc, struct ath_buf *first_bf,
static int
ath_get_aggr_limit(struct ath_softc *sc, struct ath_buf *bf)
{
int amin = 65530;
int amin = ATH_AGGR_MAXSIZE;
int i;
if (sc->sc_aggr_limit > 0 && sc->sc_aggr_limit < ATH_AGGR_MAXSIZE)
amin = sc->sc_aggr_limit;
for (i = 0; i < ATH_RC_NUM; i++) {
if (bf->bf_state.bfs_rc[i].tries == 0)
continue;
@ -488,6 +498,13 @@ ath_rateseries_setup(struct ath_softc *sc, struct ieee80211_node *ni,
* XXX It's overridden in the HAL rate scenario function
* XXX for now.
*/
/*
* XXX TODO: When the NIC is capable of three stream TX,
* transmit 1/2 stream rates on two streams.
*
* This reduces the power consumption of the NIC and
* keeps it within the PCIe slot power limits.
*/
series[i].ChSel = sc->sc_txchainmask;
if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA))

1
sys/dev/ath/if_athvar.h
View File

@ -718,6 +718,7 @@ struct ath_softc {
int sc_txchainmask; /* currently configured TX chainmask */
int sc_rxchainmask; /* currently configured RX chainmask */
int sc_rts_aggr_limit; /* TX limit on RTS aggregates */
int sc_aggr_limit; /* TX limit on all aggregates */
/* Queue limits */