Clean up some magic numbers in the DBDMA code by replacing them with
appropriately defined constants. Suggested by: gnn
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b6d213aee8
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4a8c139140
@ -93,7 +93,7 @@ int
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dbdma_resize_channel(dbdma_channel_t *chan, int newslots)
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{
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if (newslots > (PAGE_SIZE / 16))
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if (newslots > (PAGE_SIZE / sizeof(struct dbdma_command)))
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return (-1);
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chan->sc_nslots = newslots;
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@ -159,7 +159,8 @@ dbdma_run(dbdma_channel_t *chan)
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control_reg = DBDMA_STATUS_RUN | DBDMA_STATUS_PAUSE |
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DBDMA_STATUS_WAKE | DBDMA_STATUS_DEAD;
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control_reg <<= 16;
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control_reg <<= DBDMA_REG_MASK_SHIFT;
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control_reg |= DBDMA_STATUS_RUN;
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dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
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}
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@ -170,7 +171,8 @@ dbdma_pause(dbdma_channel_t *chan)
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uint32_t control_reg;
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control_reg = DBDMA_STATUS_PAUSE;
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control_reg <<= 16;
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control_reg <<= DBDMA_REG_MASK_SHIFT;
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control_reg |= DBDMA_STATUS_PAUSE;
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dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
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}
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@ -182,7 +184,8 @@ dbdma_wake(dbdma_channel_t *chan)
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control_reg = DBDMA_STATUS_WAKE | DBDMA_STATUS_PAUSE |
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DBDMA_STATUS_RUN | DBDMA_STATUS_DEAD;
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control_reg <<= 16;
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control_reg <<= DBDMA_REG_MASK_SHIFT;
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control_reg |= DBDMA_STATUS_WAKE | DBDMA_STATUS_RUN;
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dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
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}
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@ -193,7 +196,8 @@ dbdma_stop(dbdma_channel_t *chan)
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uint32_t control_reg;
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control_reg = DBDMA_STATUS_RUN;
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control_reg <<= 16;
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control_reg <<= DBDMA_REG_MASK_SHIFT;
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dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
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while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE)
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@ -205,7 +209,7 @@ dbdma_set_current_cmd(dbdma_channel_t *chan, int slot)
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{
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uint32_t cmd;
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cmd = chan->sc_slots_pa + slot * 16;
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cmd = chan->sc_slots_pa + slot * sizeof(struct dbdma_command);
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dbdma_write_reg(chan, CHAN_CMDPTR, cmd);
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}
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@ -230,7 +234,7 @@ dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, uint8_t value)
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uint32_t control_reg;
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control_reg = mask;
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control_reg <<= 16;
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control_reg <<= DBDMA_REG_MASK_SHIFT;
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control_reg |= value;
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dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
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@ -242,7 +246,8 @@ dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
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uint32_t intr_select;
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intr_select = mask;
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intr_select <<= 16;
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intr_select <<= DBDMA_REG_MASK_SHIFT;
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intr_select |= val;
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dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select);
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}
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@ -253,7 +258,8 @@ dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
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uint32_t br_select;
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br_select = mask;
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br_select <<= 16;
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br_select <<= DBDMA_REG_MASK_SHIFT;
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br_select |= val;
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dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select);
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}
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@ -264,7 +270,7 @@ dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
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uint32_t wait_select;
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wait_select = mask;
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wait_select <<= 16;
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wait_select <<= DBDMA_REG_MASK_SHIFT;
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wait_select |= val;
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dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select);
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}
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@ -286,7 +292,8 @@ dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream,
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cmd.reqCount = count;
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cmd.address = (uint32_t)(data);
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if (command != DBDMA_STORE_QUAD && command != DBDMA_LOAD_QUAD)
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cmd.cmdDep = chan->sc_slots_pa + branch_slot * 16;
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cmd.cmdDep = chan->sc_slots_pa +
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branch_slot * sizeof(struct dbdma_command);
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else
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cmd.cmdDep = branch_slot;
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@ -87,6 +87,8 @@ struct dbdma_channel {
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/* Channel control is the write channel to channel status, the upper 16 bits
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are a mask of which bytes to change */
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#define DBDMA_REG_MASK_SHIFT 16
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/* Status bits 0-7 are device dependent status bits */
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/*
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