MFC r203319:
Adds siba_bwn module which is used with bwn(4). Main purpose of this module is to distinguish parts of Silicon Backplane and of Broadcom Wireless.
This commit is contained in:
Weongyo Jeong
parent
5c07bd7cf5
commit
4b1a8666b9
sys
dev/siba
modules/siba_bwn
@ -37,9 +37,9 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/siba/sibavar.h>
|
||||
#include <dev/siba/sibareg.h>
|
||||
#include <dev/siba/siba_ids.h>
|
||||
#include <dev/siba/sibareg.h>
|
||||
#include <dev/siba/sibavar.h>
|
||||
|
||||
/*
|
||||
* TODO: De-mipsify this code.
|
||||
@ -77,7 +77,7 @@ static struct siba_devid siba_devids[] = {
|
||||
"MIPS core" },
|
||||
{ SIBA_VID_BROADCOM, SIBA_DEVID_ETHERNET, SIBA_REV_ANY,
|
||||
"Ethernet core" },
|
||||
{ SIBA_VID_BROADCOM, SIBA_DEVID_USB, SIBA_REV_ANY,
|
||||
{ SIBA_VID_BROADCOM, SIBA_DEVID_USB11_HOSTDEV, SIBA_REV_ANY,
|
||||
"USB host controller" },
|
||||
{ SIBA_VID_BROADCOM, SIBA_DEVID_IPSEC, SIBA_REV_ANY,
|
||||
"IPSEC accelerator" },
|
||||
@ -103,7 +103,6 @@ static struct siba_devid *
|
||||
static struct resource_list *
|
||||
siba_get_reslist(device_t, device_t);
|
||||
static uint8_t siba_getirq(uint16_t);
|
||||
static uint8_t siba_getncores(uint16_t);
|
||||
static int siba_print_all_resources(device_t dev);
|
||||
static int siba_print_child(device_t, device_t);
|
||||
static int siba_probe(device_t);
|
||||
@ -112,30 +111,7 @@ int siba_read_ivar(device_t, device_t, int, uintptr_t *);
|
||||
static struct siba_devinfo *
|
||||
siba_setup_devinfo(device_t, uint8_t);
|
||||
int siba_write_ivar(device_t, device_t, int, uintptr_t);
|
||||
|
||||
/*
|
||||
* Earlier ChipCommon revisions have hardcoded number of cores
|
||||
* present dependent on the ChipCommon ID.
|
||||
*/
|
||||
static uint8_t
|
||||
siba_getncores(uint16_t ccid)
|
||||
{
|
||||
uint8_t ncores;
|
||||
|
||||
switch (ccid) {
|
||||
case SIBA_CCID_SENTRY5:
|
||||
ncores = 7;
|
||||
break;
|
||||
case SIBA_CCID_BCM4710:
|
||||
case SIBA_CCID_BCM4704:
|
||||
ncores = 9;
|
||||
break;
|
||||
default:
|
||||
ncores = 0;
|
||||
}
|
||||
|
||||
return (ncores);
|
||||
}
|
||||
uint8_t siba_getncores(device_t, uint16_t);
|
||||
|
||||
/*
|
||||
* On the Sentry5, the system bus IRQs are the same as the
|
||||
@ -156,7 +132,7 @@ siba_getirq(uint16_t devid)
|
||||
case SIBA_DEVID_IPSEC:
|
||||
irq = 2;
|
||||
break;
|
||||
case SIBA_DEVID_USB:
|
||||
case SIBA_DEVID_USB11_HOSTDEV:
|
||||
irq = 3;
|
||||
break;
|
||||
case SIBA_DEVID_PCI:
|
||||
@ -188,7 +164,7 @@ siba_probe(device_t dev)
|
||||
uint16_t ccid;
|
||||
int rid;
|
||||
|
||||
sc->sc_dev = dev;
|
||||
sc->siba_dev = dev;
|
||||
|
||||
//rman_debug = 1; /* XXX */
|
||||
|
||||
@ -197,24 +173,24 @@ siba_probe(device_t dev)
|
||||
* was compiled with.
|
||||
*/
|
||||
rid = MIPS_MEM_RID;
|
||||
sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
||||
sc->siba_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
||||
RF_ACTIVE);
|
||||
if (sc->sc_mem == NULL) {
|
||||
if (sc->siba_mem_res == NULL) {
|
||||
device_printf(dev, "unable to allocate probe aperture\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
sc->sc_bt = rman_get_bustag(sc->sc_mem);
|
||||
sc->sc_bh = rman_get_bushandle(sc->sc_mem);
|
||||
sc->sc_maddr = rman_get_start(sc->sc_mem);
|
||||
sc->sc_msize = rman_get_size(sc->sc_mem);
|
||||
sc->siba_mem_bt = rman_get_bustag(sc->siba_mem_res);
|
||||
sc->siba_mem_bh = rman_get_bushandle(sc->siba_mem_res);
|
||||
sc->siba_maddr = rman_get_start(sc->siba_mem_res);
|
||||
sc->siba_msize = rman_get_size(sc->siba_mem_res);
|
||||
|
||||
if (siba_debug) {
|
||||
device_printf(dev, "start %08x len %08x\n",
|
||||
sc->sc_maddr, sc->sc_msize);
|
||||
sc->siba_maddr, sc->siba_msize);
|
||||
}
|
||||
|
||||
idlo = siba_read_4(sc, 0, SIBA_CORE_IDLO);
|
||||
idhi = siba_read_4(sc, 0, SIBA_CORE_IDHI);
|
||||
idlo = siba_mips_read_4(sc, 0, SIBA_IDLOW);
|
||||
idhi = siba_mips_read_4(sc, 0, SIBA_IDHIGH);
|
||||
ccid = ((idhi & 0x8ff0) >> 4);
|
||||
if (siba_debug) {
|
||||
device_printf(dev, "idlo = %08x\n", idlo);
|
||||
@ -256,7 +232,7 @@ siba_probe(device_t dev)
|
||||
uint16_t cc_id;
|
||||
uint16_t cc_rev;
|
||||
|
||||
ccidreg = siba_read_4(sc, 0, SIBA_CC_CCID);
|
||||
ccidreg = siba_mips_read_4(sc, 0, SIBA_CC_CHIPID);
|
||||
cc_id = (ccidreg & SIBA_CC_IDMASK);
|
||||
cc_rev = (ccidreg & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT;
|
||||
if (siba_debug) {
|
||||
@ -264,9 +240,9 @@ siba_probe(device_t dev)
|
||||
ccidreg, cc_id, cc_rev);
|
||||
}
|
||||
|
||||
sc->sc_ncores = siba_getncores(cc_id);
|
||||
sc->siba_ncores = siba_getncores(dev, cc_id);
|
||||
if (siba_debug) {
|
||||
device_printf(dev, "%d cores detected.\n", sc->sc_ncores);
|
||||
device_printf(dev, "%d cores detected.\n", sc->siba_ncores);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -275,36 +251,38 @@ siba_probe(device_t dev)
|
||||
*/
|
||||
rid = MIPS_MEM_RID;
|
||||
int result;
|
||||
result = bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->sc_mem);
|
||||
result = bus_release_resource(dev, SYS_RES_MEMORY, rid,
|
||||
sc->siba_mem_res);
|
||||
if (result != 0) {
|
||||
device_printf(dev, "error %d releasing resource\n", result);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
uint32_t total;
|
||||
total = sc->sc_ncores * SIBA_CORE_LEN;
|
||||
total = sc->siba_ncores * SIBA_CORE_LEN;
|
||||
|
||||
/* XXX Don't allocate the entire window until we
|
||||
* enumerate the bus. Once the bus has been enumerated,
|
||||
* and instance variables/children instantiated + populated,
|
||||
* release the resource so children may attach.
|
||||
*/
|
||||
sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
|
||||
sc->sc_maddr, sc->sc_maddr + total - 1, total, RF_ACTIVE);
|
||||
if (sc->sc_mem == NULL) {
|
||||
sc->siba_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
|
||||
sc->siba_maddr, sc->siba_maddr + total - 1, total, RF_ACTIVE);
|
||||
if (sc->siba_mem_res == NULL) {
|
||||
device_printf(dev, "unable to allocate entire aperture\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
sc->sc_bt = rman_get_bustag(sc->sc_mem);
|
||||
sc->sc_bh = rman_get_bushandle(sc->sc_mem);
|
||||
sc->sc_maddr = rman_get_start(sc->sc_mem);
|
||||
sc->sc_msize = rman_get_size(sc->sc_mem);
|
||||
sc->siba_mem_bt = rman_get_bustag(sc->siba_mem_res);
|
||||
sc->siba_mem_bh = rman_get_bushandle(sc->siba_mem_res);
|
||||
sc->siba_maddr = rman_get_start(sc->siba_mem_res);
|
||||
sc->siba_msize = rman_get_size(sc->siba_mem_res);
|
||||
|
||||
if (siba_debug) {
|
||||
device_printf(dev, "after remapping: start %08x len %08x\n",
|
||||
sc->sc_maddr, sc->sc_msize);
|
||||
sc->siba_maddr, sc->siba_msize);
|
||||
}
|
||||
bus_set_resource(dev, SYS_RES_MEMORY, rid, sc->sc_maddr, sc->sc_msize);
|
||||
bus_set_resource(dev, SYS_RES_MEMORY, rid, sc->siba_maddr,
|
||||
sc->siba_msize);
|
||||
|
||||
/*
|
||||
* We need a manager for the space we claim on nexus to
|
||||
@ -313,12 +291,13 @@ siba_probe(device_t dev)
|
||||
* otherwise it may be claimed elsewhere.
|
||||
* XXX move to softc
|
||||
*/
|
||||
mem_rman.rm_start = sc->sc_maddr;
|
||||
mem_rman.rm_end = sc->sc_maddr + sc->sc_msize - 1;
|
||||
mem_rman.rm_start = sc->siba_maddr;
|
||||
mem_rman.rm_end = sc->siba_maddr + sc->siba_msize - 1;
|
||||
mem_rman.rm_type = RMAN_ARRAY;
|
||||
mem_rman.rm_descr = "SiBa I/O memory addresses";
|
||||
if (rman_init(&mem_rman) != 0 ||
|
||||
rman_manage_region(&mem_rman, mem_rman.rm_start, mem_rman.rm_end) != 0) {
|
||||
rman_manage_region(&mem_rman, mem_rman.rm_start,
|
||||
mem_rman.rm_end) != 0) {
|
||||
panic("%s: mem_rman", __func__);
|
||||
}
|
||||
|
||||
@ -344,7 +323,7 @@ siba_attach(device_t dev)
|
||||
* NB: only one core may be mapped at any time if the siba bus
|
||||
* is the child of a PCI or PCMCIA bus.
|
||||
*/
|
||||
for (idx = 0; idx < sc->sc_ncores; idx++) {
|
||||
for (idx = 0; idx < sc->siba_ncores; idx++) {
|
||||
sdi = siba_setup_devinfo(dev, idx);
|
||||
child = device_add_child(dev, NULL, -1);
|
||||
if (child == NULL)
|
||||
@ -483,13 +462,14 @@ siba_setup_devinfo(device_t dev, uint8_t idx)
|
||||
sdi = malloc(sizeof(*sdi), M_DEVBUF, M_WAITOK | M_ZERO);
|
||||
resource_list_init(&sdi->sdi_rl);
|
||||
|
||||
idlo = siba_read_4(sc, idx, SIBA_CORE_IDLO);
|
||||
idhi = siba_read_4(sc, idx, SIBA_CORE_IDHI);
|
||||
idlo = siba_mips_read_4(sc, idx, SIBA_IDLOW);
|
||||
idhi = siba_mips_read_4(sc, idx, SIBA_IDHIGH);
|
||||
|
||||
vendorid = (idhi & SIBA_IDHIGH_VC) >> SIBA_IDHIGH_VC_SHIFT;
|
||||
vendorid = (idhi & SIBA_IDHIGH_VENDORMASK) >>
|
||||
SIBA_IDHIGH_VENDOR_SHIFT;
|
||||
devid = ((idhi & 0x8ff0) >> 4);
|
||||
rev = (idhi & SIBA_IDHIGH_RCLO);
|
||||
rev |= (idhi & SIBA_IDHIGH_RCHI) >> SIBA_IDHIGH_RCHI_SHIFT;
|
||||
rev = (idhi & SIBA_IDHIGH_REVLO);
|
||||
rev |= (idhi & SIBA_IDHIGH_REVHI) >> SIBA_IDHIGH_REVHI_SHIFT;
|
||||
|
||||
sdi->sdi_vid = vendorid;
|
||||
sdi->sdi_devid = devid;
|
||||
@ -500,7 +480,7 @@ siba_setup_devinfo(device_t dev, uint8_t idx)
|
||||
/*
|
||||
* Determine memory window on bus and irq if one is needed.
|
||||
*/
|
||||
baseaddr = sc->sc_maddr + (idx * SIBA_CORE_LEN);
|
||||
baseaddr = sc->siba_maddr + (idx * SIBA_CORE_LEN);
|
||||
resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY,
|
||||
MIPS_MEM_RID, /* XXX */
|
||||
baseaddr, baseaddr + SIBA_CORE_LEN - 1, SIBA_CORE_LEN);
|
||||
|
||||
366
sys/dev/siba/siba_bwn.c
Normal file
366
sys/dev/siba/siba_bwn.c
Normal file
@ -0,0 +1,366 @@
|
||||
/*-
|
||||
* Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer,
|
||||
* without modification.
|
||||
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
|
||||
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
|
||||
* redistribution must be conditioned upon including a substantially
|
||||
* similar Disclaimer requirement for further binary redistribution.
|
||||
*
|
||||
* NO WARRANTY
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
|
||||
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
|
||||
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* Sonics Silicon Backplane front-end for bwn(4).
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/errno.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/socket.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
#include <net/if_arp.h>
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
|
||||
#include <dev/siba/siba_ids.h>
|
||||
#include <dev/siba/sibareg.h>
|
||||
#include <dev/siba/sibavar.h>
|
||||
|
||||
/*
|
||||
* PCI glue.
|
||||
*/
|
||||
|
||||
struct siba_bwn_softc {
|
||||
/* Child driver using MSI. */
|
||||
device_t ssc_msi_child;
|
||||
struct siba_softc ssc_siba;
|
||||
};
|
||||
|
||||
#define BS_BAR 0x10
|
||||
#define PCI_VENDOR_BROADCOM 0x14e4
|
||||
#define N(a) (sizeof(a) / sizeof(a[0]))
|
||||
|
||||
static const struct siba_dev {
|
||||
uint16_t vid;
|
||||
uint16_t did;
|
||||
const char *desc;
|
||||
} siba_devices[] = {
|
||||
{ PCI_VENDOR_BROADCOM, 0x4301, "Broadcom BCM4301 802.11b Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4306, "Unknown" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4307, "Broadcom BCM4307 802.11b Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4311, "Broadcom BCM4311 802.11b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4312,
|
||||
"Broadcom BCM4312 802.11a/b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4315, "Broadcom BCM4312 802.11b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4318, "Broadcom BCM4318 802.11b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4319,
|
||||
"Broadcom BCM4318 802.11a/b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4320, "Broadcom BCM4306 802.11b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4321, "Broadcom BCM4306 802.11a Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4324,
|
||||
"Broadcom BCM4309 802.11a/b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4325, "Broadcom BCM4306 802.11b/g Wireless" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4328, "Unknown" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x4329, "Unknown" },
|
||||
{ PCI_VENDOR_BROADCOM, 0x432b, "Unknown" }
|
||||
};
|
||||
|
||||
device_t siba_add_child(device_t, struct siba_softc *, int, const char *,
|
||||
int);
|
||||
int siba_core_attach(struct siba_softc *);
|
||||
int siba_core_detach(struct siba_softc *);
|
||||
int siba_core_suspend(struct siba_softc *);
|
||||
int siba_core_resume(struct siba_softc *);
|
||||
|
||||
static int
|
||||
siba_bwn_probe(device_t dev)
|
||||
{
|
||||
int i;
|
||||
uint16_t did, vid;
|
||||
|
||||
did = pci_get_device(dev);
|
||||
vid = pci_get_vendor(dev);
|
||||
|
||||
for (i = 0; i < N(siba_devices); i++) {
|
||||
if (siba_devices[i].did == did && siba_devices[i].vid == vid) {
|
||||
device_set_desc(dev, siba_devices[i].desc);
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_attach(device_t dev)
|
||||
{
|
||||
struct siba_bwn_softc *ssc = device_get_softc(dev);
|
||||
struct siba_softc *siba = &ssc->ssc_siba;
|
||||
|
||||
siba->siba_dev = dev;
|
||||
siba->siba_type = SIBA_TYPE_PCI;
|
||||
|
||||
/*
|
||||
* Enable bus mastering.
|
||||
*/
|
||||
pci_enable_busmaster(dev);
|
||||
|
||||
/*
|
||||
* Setup memory-mapping of PCI registers.
|
||||
*/
|
||||
siba->siba_mem_rid = SIBA_PCIR_BAR;
|
||||
siba->siba_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
||||
&siba->siba_mem_rid, RF_ACTIVE);
|
||||
if (siba->siba_mem_res == NULL) {
|
||||
device_printf(dev, "cannot map register space\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
siba->siba_mem_bt = rman_get_bustag(siba->siba_mem_res);
|
||||
siba->siba_mem_bh = rman_get_bushandle(siba->siba_mem_res);
|
||||
|
||||
/* Get more PCI information */
|
||||
siba->siba_pci_did = pci_get_device(dev);
|
||||
siba->siba_pci_vid = pci_get_vendor(dev);
|
||||
siba->siba_pci_subvid = pci_get_subvendor(dev);
|
||||
siba->siba_pci_subdid = pci_get_subdevice(dev);
|
||||
|
||||
return (siba_core_attach(siba));
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_detach(device_t dev)
|
||||
{
|
||||
struct siba_bwn_softc *ssc = device_get_softc(dev);
|
||||
struct siba_softc *siba = &ssc->ssc_siba;
|
||||
|
||||
/* check if device was removed */
|
||||
siba->siba_invalid = !bus_child_present(dev);
|
||||
|
||||
pci_disable_busmaster(dev);
|
||||
bus_generic_detach(dev);
|
||||
siba_core_detach(siba);
|
||||
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, siba->siba_mem_res);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_shutdown(device_t dev)
|
||||
{
|
||||
device_t *devlistp;
|
||||
int devcnt, error = 0, i;
|
||||
|
||||
error = device_get_children(dev, &devlistp, &devcnt);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
|
||||
for (i = 0 ; i < devcnt ; i++)
|
||||
device_shutdown(devlistp[i]);
|
||||
free(devlistp, M_TEMP);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_suspend(device_t dev)
|
||||
{
|
||||
struct siba_bwn_softc *ssc = device_get_softc(dev);
|
||||
struct siba_softc *siba = &ssc->ssc_siba;
|
||||
device_t *devlistp;
|
||||
int devcnt, error = 0, i, j;
|
||||
|
||||
error = device_get_children(dev, &devlistp, &devcnt);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
|
||||
for (i = 0 ; i < devcnt ; i++) {
|
||||
error = DEVICE_SUSPEND(devlistp[i]);
|
||||
if (error) {
|
||||
for (j = 0; j < i; i++)
|
||||
DEVICE_RESUME(devlistp[j]);
|
||||
return (error);
|
||||
}
|
||||
}
|
||||
free(devlistp, M_TEMP);
|
||||
return (siba_core_suspend(siba));
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_resume(device_t dev)
|
||||
{
|
||||
struct siba_bwn_softc *ssc = device_get_softc(dev);
|
||||
struct siba_softc *siba = &ssc->ssc_siba;
|
||||
device_t *devlistp;
|
||||
int devcnt, error = 0, i;
|
||||
|
||||
error = siba_core_resume(siba);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
|
||||
error = device_get_children(dev, &devlistp, &devcnt);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
|
||||
for (i = 0 ; i < devcnt ; i++)
|
||||
DEVICE_RESUME(devlistp[i]);
|
||||
free(devlistp, M_TEMP);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_t
|
||||
siba_bwn_add_child(device_t dev, int order, const char *name, int unit)
|
||||
{
|
||||
struct siba_bwn_softc *ssc = device_get_softc(dev);
|
||||
struct siba_softc *siba = &ssc->ssc_siba;
|
||||
|
||||
return (siba_add_child(dev, siba, order, name, unit));
|
||||
}
|
||||
|
||||
/* proxying to the parent */
|
||||
static struct resource *
|
||||
siba_bwn_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
|
||||
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
|
||||
type, rid, start, end, count, flags));
|
||||
}
|
||||
|
||||
/* proxying to the parent */
|
||||
static int
|
||||
siba_bwn_release_resource(device_t dev, device_t child, int type,
|
||||
int rid, struct resource *r)
|
||||
{
|
||||
|
||||
return (BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, type,
|
||||
rid, r));
|
||||
}
|
||||
|
||||
/* proxying to the parent */
|
||||
static int
|
||||
siba_bwn_setup_intr(device_t dev, device_t child, struct resource *irq,
|
||||
int flags, driver_filter_t *filter, driver_intr_t *intr, void *arg,
|
||||
void **cookiep)
|
||||
{
|
||||
|
||||
return (BUS_SETUP_INTR(device_get_parent(dev), dev, irq, flags,
|
||||
filter, intr, arg, cookiep));
|
||||
}
|
||||
|
||||
/* proxying to the parent */
|
||||
static int
|
||||
siba_bwn_teardown_intr(device_t dev, device_t child, struct resource *irq,
|
||||
void *cookie)
|
||||
{
|
||||
|
||||
return (BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie));
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_find_extcap(device_t dev, device_t child, int capability,
|
||||
int *capreg)
|
||||
{
|
||||
|
||||
return (pci_find_extcap(dev, capability, capreg));
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_alloc_msi(device_t dev, device_t child, int *count)
|
||||
{
|
||||
struct siba_bwn_softc *ssc;
|
||||
int error;
|
||||
|
||||
ssc = device_get_softc(dev);
|
||||
if (ssc->ssc_msi_child != NULL)
|
||||
return (EBUSY);
|
||||
error = pci_alloc_msi(dev, count);
|
||||
if (error == 0)
|
||||
ssc->ssc_msi_child = child;
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_release_msi(device_t dev, device_t child)
|
||||
{
|
||||
struct siba_bwn_softc *ssc;
|
||||
int error;
|
||||
|
||||
ssc = device_get_softc(dev);
|
||||
if (ssc->ssc_msi_child != child)
|
||||
return (ENXIO);
|
||||
error = pci_release_msi(dev);
|
||||
if (error == 0)
|
||||
ssc->ssc_msi_child = NULL;
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
siba_bwn_msi_count(device_t dev, device_t child)
|
||||
{
|
||||
|
||||
return (pci_msi_count(dev));
|
||||
}
|
||||
|
||||
static device_method_t siba_bwn_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, siba_bwn_probe),
|
||||
DEVMETHOD(device_attach, siba_bwn_attach),
|
||||
DEVMETHOD(device_detach, siba_bwn_detach),
|
||||
DEVMETHOD(device_shutdown, siba_bwn_shutdown),
|
||||
DEVMETHOD(device_suspend, siba_bwn_suspend),
|
||||
DEVMETHOD(device_resume, siba_bwn_resume),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_add_child, siba_bwn_add_child),
|
||||
DEVMETHOD(bus_alloc_resource, siba_bwn_alloc_resource),
|
||||
DEVMETHOD(bus_release_resource, siba_bwn_release_resource),
|
||||
DEVMETHOD(bus_setup_intr, siba_bwn_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, siba_bwn_teardown_intr),
|
||||
|
||||
/* PCI interface */
|
||||
DEVMETHOD(pci_find_extcap, siba_bwn_find_extcap),
|
||||
DEVMETHOD(pci_alloc_msi, siba_bwn_alloc_msi),
|
||||
DEVMETHOD(pci_release_msi, siba_bwn_release_msi),
|
||||
DEVMETHOD(pci_msi_count, siba_bwn_msi_count),
|
||||
|
||||
{ 0,0 }
|
||||
};
|
||||
static driver_t siba_bwn_driver = {
|
||||
"siba_bwn",
|
||||
siba_bwn_methods,
|
||||
sizeof(struct siba_bwn_softc)
|
||||
};
|
||||
static devclass_t siba_bwn_devclass;
|
||||
DRIVER_MODULE(siba_bwn, pci, siba_bwn_driver, siba_bwn_devclass, 0, 0);
|
||||
MODULE_VERSION(siba_bwn, 1);
|
||||
@ -55,9 +55,9 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/siba/sibavar.h>
|
||||
#include <dev/siba/sibareg.h>
|
||||
#include <dev/siba/siba_ids.h>
|
||||
#include <dev/siba/sibareg.h>
|
||||
#include <dev/siba/sibavar.h>
|
||||
|
||||
static int siba_cc_attach(device_t);
|
||||
static int siba_cc_probe(device_t);
|
||||
|
||||
2007
sys/dev/siba/siba_core.c
Normal file
2007
sys/dev/siba/siba_core.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -39,23 +39,45 @@ struct siba_devid {
|
||||
uint8_t sd_rev;
|
||||
char *sd_desc;
|
||||
};
|
||||
#define SIBA_DEV(_vendor, _cid, _rev, _msg) \
|
||||
{ SIBA_VID_##_vendor, SIBA_DEVID_##_cid, _rev, _msg }
|
||||
|
||||
/*
|
||||
* Device IDs
|
||||
*/
|
||||
#define SIBA_DEVID_ANY 0xffff
|
||||
#define SIBA_DEVID_CHIPCOMMON 0x0800
|
||||
#define SIBA_DEVID_INSIDELINE 0x0801
|
||||
#define SIBA_DEVID_SDRAM 0x0803
|
||||
#define SIBA_DEVID_PCI 0x0804
|
||||
#define SIBA_DEVID_MIPS 0x0805
|
||||
#define SIBA_DEVID_ETHERNET 0x0806
|
||||
#define SIBA_DEVID_MODEM 0x0807
|
||||
#define SIBA_DEVID_USB 0x0808
|
||||
#define SIBA_DEVID_IPSEC 0x080b
|
||||
#define SIBA_DEVID_SDRAMDDR 0x080f
|
||||
#define SIBA_DEVID_EXTIF 0x0811
|
||||
#define SIBA_DEVID_MIPS_3302 0x0816
|
||||
#define SIBA_DEVID_CHIPCOMMON 0x800
|
||||
#define SIBA_DEVID_ILINE20 0x801
|
||||
#define SIBA_DEVID_SDRAM 0x803
|
||||
#define SIBA_DEVID_PCI 0x804
|
||||
#define SIBA_DEVID_MIPS 0x805
|
||||
#define SIBA_DEVID_ETHERNET 0x806
|
||||
#define SIBA_DEVID_MODEM 0x807
|
||||
#define SIBA_DEVID_USB11_HOSTDEV 0x808
|
||||
#define SIBA_DEVID_ADSL 0x809
|
||||
#define SIBA_DEVID_ILINE100 0x80a
|
||||
#define SIBA_DEVID_IPSEC 0x80b
|
||||
#define SIBA_DEVID_PCMCIA 0x80d
|
||||
#define SIBA_DEVID_INTERNAL_MEM 0x80e
|
||||
#define SIBA_DEVID_SDRAMDDR 0x80f
|
||||
#define SIBA_DEVID_EXTIF 0x811
|
||||
#define SIBA_DEVID_80211 0x812
|
||||
#define SIBA_DEVID_MIPS_3302 0x816
|
||||
#define SIBA_DEVID_USB11_HOST 0x817
|
||||
#define SIBA_DEVID_USB11_DEV 0x818
|
||||
#define SIBA_DEVID_USB20_HOST 0x819
|
||||
#define SIBA_DEVID_USB20_DEV 0x81a
|
||||
#define SIBA_DEVID_SDIO_HOST 0x81b
|
||||
#define SIBA_DEVID_ROBOSWITCH 0x81c
|
||||
#define SIBA_DEVID_PARA_ATA 0x81d
|
||||
#define SIBA_DEVID_SATA_XORDMA 0x81e
|
||||
#define SIBA_DEVID_ETHERNET_GBIT 0x81f
|
||||
#define SIBA_DEVID_PCIE 0x820
|
||||
#define SIBA_DEVID_MIMO_PHY 0x821
|
||||
#define SIBA_DEVID_SRAM_CTRLR 0x822
|
||||
#define SIBA_DEVID_MINI_MACPHY 0x823
|
||||
#define SIBA_DEVID_ARM_1176 0x824
|
||||
#define SIBA_DEVID_ARM_7TDMI 0x825
|
||||
|
||||
/*
|
||||
* Vendor IDs
|
||||
|
||||
@ -55,9 +55,9 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
#include "pcib_if.h"
|
||||
|
||||
#include <dev/siba/sibavar.h>
|
||||
#include <dev/siba/sibareg.h>
|
||||
#include <dev/siba/siba_ids.h>
|
||||
#include <dev/siba/sibareg.h>
|
||||
#include <dev/siba/sibavar.h>
|
||||
#include <dev/siba/siba_pcibvar.h>
|
||||
|
||||
#ifndef MIPS_MEM_RID
|
||||
@ -79,10 +79,6 @@ __FBSDID("$FreeBSD$");
|
||||
#define SBPCI_CFGBASE 0x0C000000
|
||||
#define SBPCI_CFGSIZE 0x01000000
|
||||
|
||||
#define SBPCI_SBTOPCI0 0x100
|
||||
#define SBPCI_SBTOPCI1 0x104
|
||||
#define SBPCI_SBTOPCI2 0x108
|
||||
|
||||
/*
|
||||
* TODO: implement type 1 config space access (ie beyond bus 0)
|
||||
* we may need to tweak the windows to do this
|
||||
@ -187,9 +183,12 @@ siba_pcib_attach(device_t dev)
|
||||
* XXX we need to be able to do type 1 too.
|
||||
* we probably don't need to be able to do i/o cycles.
|
||||
*/
|
||||
SBPCI_WRITE_4(sc, SBPCI_SBTOPCI0, 1); /* I/O read/write window */
|
||||
SBPCI_WRITE_4(sc, SBPCI_SBTOPCI1, 2); /* type 0 configuration only */
|
||||
SBPCI_WRITE_4(sc, SBPCI_SBTOPCI2, 1 << 30); /* memory only */
|
||||
|
||||
/* I/O read/write window */
|
||||
SBPCI_WRITE_4(sc, SIBA_PCICORE_SBTOPCI0, 1);
|
||||
/* type 0 configuration only */
|
||||
SBPCI_WRITE_4(sc, SIBA_PCICORE_SBTOPCI1, 2);
|
||||
SBPCI_WRITE_4(sc, SIBA_PCICORE_SBTOPCI2, 1 << 30); /* memory only */
|
||||
DELAY(500);
|
||||
|
||||
/* XXX resource managers */
|
||||
@ -365,7 +364,7 @@ siba_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
|
||||
/*
|
||||
* The configuration tag on the broadcom is weird.
|
||||
*/
|
||||
SBPCI_WRITE_4(sc, SBPCI_SBTOPCI1, 2); /* XXX again??? */
|
||||
SBPCI_WRITE_4(sc, SIBA_PCICORE_SBTOPCI1, 2); /* XXX again??? */
|
||||
cfgtag = ((1 << slot) << 16) | (func << 8);
|
||||
cfgaddr = SBPCI_CFGBASE | cfgtag | (reg & ~3);
|
||||
|
||||
|
||||
@ -34,40 +34,383 @@
|
||||
#ifndef _SIBA_SIBAREG_H_
|
||||
#define _SIBA_SIBAREG_H_
|
||||
|
||||
#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */
|
||||
#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */
|
||||
#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */
|
||||
|
||||
/* offset of high ID register */
|
||||
#define SIBA_CORE_IDLO 0x00000ff8
|
||||
#define SIBA_CORE_IDHI 0x00000ffc
|
||||
|
||||
/*
|
||||
* Offsets of ChipCommon core registers.
|
||||
* XXX: move to siba_cc
|
||||
*/
|
||||
#define SIBA_CC_UART0 0x00000300 /* offset of UART0 */
|
||||
#define SIBA_CC_UART1 0x00000400 /* offset of UART1 */
|
||||
|
||||
#define SIBA_CC_CCID 0x0000
|
||||
#define SIBA_CC_IDMASK 0x0000FFFF
|
||||
#define SIBA_CC_REVMASK 0x000F0000
|
||||
#define SIBA_CC_REVSHIFT 16
|
||||
#define SIBA_CC_PACKMASK 0x00F00000
|
||||
#define SIBA_CC_PACKSHIFT 20
|
||||
#define SIBA_CC_NRCORESMASK 0x0F000000
|
||||
#define SIBA_CC_NRCORESSHIFT 24
|
||||
|
||||
#define SIBA_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */
|
||||
#define SIBA_IDHIGH_CC 0x00008FF0 /* Core Code */
|
||||
#define SIBA_IDHIGH_CC_SHIFT 4
|
||||
#define SIBA_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */
|
||||
#define SIBA_IDHIGH_RCHI_SHIFT 8
|
||||
#define SIBA_IDHIGH_VC 0xFFFF0000 /* Vendor Code */
|
||||
#define SIBA_IDHIGH_VC_SHIFT 16
|
||||
|
||||
#define PCI_DEVICE_ID_BCM4401 0x4401
|
||||
#define PCI_DEVICE_ID_BCM4401B0 0x4402
|
||||
#define PCI_DEVICE_ID_BCM4401B1 0x170c
|
||||
#define SIBA_PCIR_BAR PCIR_BAR(0)
|
||||
#define SIBA_CCID_BCM4710 0x4710
|
||||
#define SIBA_CCID_BCM4704 0x4704
|
||||
#define SIBA_CCID_SENTRY5 0x5365
|
||||
|
||||
/*
|
||||
* ChipCommon registers.
|
||||
*/
|
||||
#define SIBA_CC_CHIPID 0x0000
|
||||
#define SIBA_CC_IDMASK 0x0000ffff
|
||||
#define SIBA_CC_ID(id) (id & SIBA_CC_IDMASK)
|
||||
#define SIBA_CC_REVMASK 0x000f0000
|
||||
#define SIBA_CC_REVSHIFT 16
|
||||
#define SIBA_CC_REV(id) \
|
||||
((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT)
|
||||
#define SIBA_CC_PKGMASK 0x00F00000
|
||||
#define SIBA_CC_PKGSHIFT 20
|
||||
#define SIBA_CC_PKG(id) \
|
||||
((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT)
|
||||
#define SIBA_CC_NCORESMASK 0x0F000000
|
||||
#define SIBA_CC_NCORESSHIFT 24
|
||||
#define SIBA_CC_NCORES(id) \
|
||||
((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT)
|
||||
#define SIBA_CC_CAPS 0x0004
|
||||
#define SIBA_CC_CAPS_PWCTL 0x00040000
|
||||
#define SIBA_CC_CAPS_PMU 0x10000000 /* PMU (rev >= 20) */
|
||||
#define SIBA_CC_CHIPCTL 0x0028 /* rev >= 11 */
|
||||
#define SIBA_CC_CHIPSTAT 0x002C /* rev >= 11 */
|
||||
#define SIBA_CC_BCAST_ADDR 0x0050 /* Broadcast Address */
|
||||
#define SIBA_CC_BCAST_DATA 0x0054 /* Broadcast Data */
|
||||
#define SIBA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
|
||||
#define SIBA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
|
||||
#define SIBA_CC_CLKSLOW 0x00b8 /* 6 <= Rev <= 9 only */
|
||||
#define SIBA_CC_CLKSLOW_SRC 0x00000007
|
||||
#define SIBA_CC_CLKSLOW_SRC_CRYSTAL 0x00000001
|
||||
#define SIBA_CC_CLKSLOW_FSLOW 0x00000800
|
||||
#define SIBA_CC_CLKSLOW_IPLL 0x00001000
|
||||
#define SIBA_CC_CLKSLOW_ENXTAL 0x00002000
|
||||
#define SIBA_CC_CLKSYSCTL 0x00C0 /* Rev >= 3 only */
|
||||
#define SIBA_CC_CLKCTLSTATUS 0x01e0
|
||||
#define SIBA_CC_CLKCTLSTATUS_HT 0x00010000
|
||||
#define SIBA_CC_UART0 0x0300 /* offset of UART0 */
|
||||
#define SIBA_CC_UART1 0x0400 /* offset of UART1 */
|
||||
#define SIBA_CC_PMUCTL 0x0600 /* PMU control */
|
||||
#define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */
|
||||
#define SIBA_CC_PMUCTL_NOILP 0x00000200
|
||||
#define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq */
|
||||
#define SIBA_CC_PMUCTL_XF_VAL(id) ((id & 0x0000007c) >> 2)
|
||||
#define SIBA_CC_PMUCAPS 0x0604
|
||||
#define SIBA_CC_PMUCAPS_REV 0x000000ff
|
||||
#define SIBA_CC_PMU_MINRES 0x0618
|
||||
#define SIBA_CC_PMU_MAXRES 0x061c
|
||||
#define SIBA_CC_PMU_TABSEL 0x0620
|
||||
#define SIBA_CC_PMU_DEPMSK 0x0624
|
||||
#define SIBA_CC_PMU_UPDNTM 0x0628
|
||||
#define SIBA_CC_PLLCTL_ADDR 0x0660
|
||||
#define SIBA_CC_PLLCTL_DATA 0x0664
|
||||
|
||||
#define SIBA_CC_PMU0_PLL0 0
|
||||
#define SIBA_CC_PMU0_PLL0_PDIV_MSK 0x00000001
|
||||
#define SIBA_CC_PMU0_PLL0_PDIV_FREQ 25000
|
||||
#define SIBA_CC_PMU0_PLL1 1
|
||||
#define SIBA_CC_PMU0_PLL1_IMSK 0xf0000000
|
||||
#define SIBA_CC_PMU0_PLL1_FMSK 0x0fffff00
|
||||
#define SIBA_CC_PMU0_PLL1_STOPMOD 0x00000040
|
||||
#define SIBA_CC_PMU0_PLL2 2
|
||||
#define SIBA_CC_PMU0_PLL2_IMSKHI 0x0000000f
|
||||
#define SIBA_CC_PMU1_PLL0 0
|
||||
#define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000
|
||||
#define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000
|
||||
#define SIBA_CC_PMU1_PLL2 2
|
||||
#define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000
|
||||
#define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000
|
||||
#define SIBA_CC_PMU1_PLL3 3
|
||||
#define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff
|
||||
#define SIBA_CC_PMU1_PLL5 5
|
||||
#define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00
|
||||
|
||||
#define SIBA_CC_PMU0_DEFAULT_XTALFREQ 20000
|
||||
#define SIBA_CC_PMU1_DEFAULT_FREQ 15360
|
||||
|
||||
#define SIBA_CC_PMU1_PLLTAB_ENTRY \
|
||||
{ \
|
||||
{ 12000, 1, 3, 22, 0x9, 0xffffef }, \
|
||||
{ 13000, 2, 1, 6, 0xb, 0x483483 }, \
|
||||
{ 14400, 3, 1, 10, 0xa, 0x1c71c7 }, \
|
||||
{ 15360, 4, 1, 5, 0xb, 0x755555 }, \
|
||||
{ 16200, 5, 1, 10, 0x5, 0x6e9e06 }, \
|
||||
{ 16800, 6, 1, 10, 0x5, 0x3cf3cf }, \
|
||||
{ 19200, 7, 1, 9, 0x5, 0x17b425 }, \
|
||||
{ 19800, 8, 1, 11, 0x4, 0xa57eb }, \
|
||||
{ 20000, 9, 1, 11, 0x4, 0 }, \
|
||||
{ 24000, 10, 3, 11, 0xa, 0 }, \
|
||||
{ 25000, 11, 5, 16, 0xb, 0 }, \
|
||||
{ 26000, 12, 1, 2, 0x10, 0xec4ec4 }, \
|
||||
{ 30000, 13, 3, 8, 0xb, 0 }, \
|
||||
{ 38400, 14, 1, 5, 0x4, 0x955555 }, \
|
||||
{ 40000, 15, 1, 2, 0xb, 0 } \
|
||||
}
|
||||
|
||||
#define SIBA_CC_PMU0_PLLTAB_ENTRY \
|
||||
{ \
|
||||
{ 12000, 1, 73, 349525, }, { 13000, 2, 67, 725937, }, \
|
||||
{ 14400, 3, 61, 116508, }, { 15360, 4, 57, 305834, }, \
|
||||
{ 16200, 5, 54, 336579, }, { 16800, 6, 52, 399457, }, \
|
||||
{ 19200, 7, 45, 873813, }, { 19800, 8, 44, 466033, }, \
|
||||
{ 20000, 9, 44, 0, }, { 25000, 10, 70, 419430, }, \
|
||||
{ 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, }, \
|
||||
{ 38400, 13, 45, 873813, }, { 40000, 14, 45, 0, }, \
|
||||
}
|
||||
|
||||
#define SIBA_CC_PMU_4325_BURST 1
|
||||
#define SIBA_CC_PMU_4325_CLBURST 3
|
||||
#define SIBA_CC_PMU_4325_LN 10
|
||||
#define SIBA_CC_PMU_4325_CRYSTAL 13
|
||||
#define SIBA_CC_PMU_4325_RX_PWR 15
|
||||
#define SIBA_CC_PMU_4325_TX_PWR 16
|
||||
#define SIBA_CC_PMU_4325_LOGEN_PWR 18
|
||||
#define SIBA_CC_PMU_4325_AFE_PWR 19
|
||||
#define SIBA_CC_PMU_4325_BBPLL_PWR 20
|
||||
#define SIBA_CC_PMU_4325_HT 21
|
||||
#define SIBA_CC_PMU_4328_EXT_SWITCH_PWM 0
|
||||
#define SIBA_CC_PMU_4328_BB_SWITCH_PWM 1
|
||||
#define SIBA_CC_PMU_4328_BB_SWITCH_BURST 2
|
||||
#define SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST 3
|
||||
#define SIBA_CC_PMU_4328_ILP_REQUEST 4
|
||||
#define SIBA_CC_PMU_4328_RADSWITCH_PWM 5 /* radio switch */
|
||||
#define SIBA_CC_PMU_4328_RADSWITCH_BURST 6
|
||||
#define SIBA_CC_PMU_4328_ROM_SWITCH 7
|
||||
#define SIBA_CC_PMU_4328_PA_REF 8
|
||||
#define SIBA_CC_PMU_4328_RADIO 9
|
||||
#define SIBA_CC_PMU_4328_AFE 10
|
||||
#define SIBA_CC_PMU_4328_PLL 11
|
||||
#define SIBA_CC_PMU_4328_BG_FILTBYP 12
|
||||
#define SIBA_CC_PMU_4328_TX_FILTBYP 13
|
||||
#define SIBA_CC_PMU_4328_RX_FILTBYP 14
|
||||
#define SIBA_CC_PMU_4328_CRYSTAL_PU 15
|
||||
#define SIBA_CC_PMU_4328_CRYSTAL_EN 16
|
||||
#define SIBA_CC_PMU_4328_BB_PLL_FILTBYP 17
|
||||
#define SIBA_CC_PMU_4328_RF_PLL_FILTBYP 18
|
||||
#define SIBA_CC_PMU_4328_BB_PLL_PU 19
|
||||
#define SIBA_CC_PMU_5354_BB_PLL_PU 19
|
||||
|
||||
#define SIBA_CC_PMU_4325_RES_UPDOWN \
|
||||
{ \
|
||||
{ SIBA_CC_PMU_4325_CRYSTAL, 0x1501 } \
|
||||
}
|
||||
|
||||
#define SIBA_CC_PMU_4325_RES_DEPEND \
|
||||
{ \
|
||||
{ SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD, \
|
||||
((1 << SIBA_CC_PMU_4325_RX_PWR) | \
|
||||
(1 << SIBA_CC_PMU_4325_TX_PWR) | \
|
||||
(1 << SIBA_CC_PMU_4325_LOGEN_PWR) | \
|
||||
(1 << SIBA_CC_PMU_4325_AFE_PWR)) } \
|
||||
}
|
||||
|
||||
#define SIBA_CC_PMU_4328_RES_UPDOWN \
|
||||
{ \
|
||||
{ SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 }, \
|
||||
{ SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f }, \
|
||||
{ SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 }, \
|
||||
{ SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 }, \
|
||||
{ SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 }, \
|
||||
{ SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_PA_REF, 0x0f01 }, \
|
||||
{ SIBA_CC_PMU_4328_RADIO, 0x0f01 }, \
|
||||
{ SIBA_CC_PMU_4328_AFE, 0x0f01 }, \
|
||||
{ SIBA_CC_PMU_4328_PLL, 0x0f01 }, \
|
||||
{ SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 }, \
|
||||
{ SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 }, \
|
||||
{ SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 }, \
|
||||
}
|
||||
|
||||
#define SIBA_CC_PMU_4328_RES_DEPEND \
|
||||
{ \
|
||||
{ SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET, \
|
||||
((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | \
|
||||
(1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) }, \
|
||||
}
|
||||
|
||||
#define SIBA_CC_CHST_4325_PMUTOP_2B 0x00000200
|
||||
|
||||
#define SIBA_BAR0 0x80
|
||||
#define SIBA_IRQMASK 0x94
|
||||
#define SIBA_GPIO_IN 0xb0
|
||||
#define SIBA_GPIO_OUT 0xb4
|
||||
#define SIBA_GPIO_OUT_EN 0xb8
|
||||
#define SIBA_GPIO_CRYSTAL 0x40
|
||||
#define SIBA_GPIO_PLL 0x80
|
||||
|
||||
#define SIBA_REGWIN(x) \
|
||||
(SIBA_ENUM_START + ((x) * SIBA_CORE_LEN))
|
||||
#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */
|
||||
#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */
|
||||
#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */
|
||||
#define SIBA_ENUM_START 0x18000000U
|
||||
#define SIBA_ENUM_END 0x18010000U
|
||||
|
||||
#define SIBA_DMA_TRANSLATION_MASK 0xc0000000
|
||||
|
||||
#define SIBA_PCI_DMA 0x40000000U
|
||||
#define SIBA_TPS 0x0f18
|
||||
#define SIBA_TPS_BPFLAG 0x0000003f
|
||||
#define SIBA_IAS 0x0f90 /* Initiator Agent State */
|
||||
#define SIBA_IAS_INBAND_ERR 0x00020000
|
||||
#define SIBA_IAS_TIMEOUT 0x00040000
|
||||
#define SIBA_INTR_MASK 0x0f94
|
||||
#define SIBA_TGSLOW 0x0f98
|
||||
#define SIBA_TGSLOW_RESET 0x00000001 /* target state low */
|
||||
#define SIBA_TGSLOW_REJECT_22 0x00000002
|
||||
#define SIBA_TGSLOW_REJECT_23 0x00000004
|
||||
#define SIBA_TGSLOW_CLOCK 0x00010000
|
||||
#define SIBA_TGSLOW_FGC 0x00020000
|
||||
#define SIBA_TGSHIGH 0x0f9c
|
||||
#define SIBA_TGSHIGH_SERR 0x00000001
|
||||
#define SIBA_TGSHIGH_BUSY 0x00000004
|
||||
#define SIBA_TGSHIGH_DMA64 0x10000000
|
||||
#define SIBA_IMCFGLO 0x0fa8
|
||||
#define SIBA_IMCFGLO_SERTO 0x00000007
|
||||
#define SIBA_IMCFGLO_REQTO 0x00000070
|
||||
#define SIBA_IDLOW 0x0ff8
|
||||
#define SIBA_IDLOW_SSBREV 0xf0000000
|
||||
#define SIBA_IDLOW_SSBREV_22 0x00000000
|
||||
#define SIBA_IDLOW_SSBREV_23 0x10000000
|
||||
#define SIBA_IDLOW_SSBREV_24 0x40000000
|
||||
#define SIBA_IDLOW_SSBREV_25 0x50000000
|
||||
#define SIBA_IDLOW_SSBREV_26 0x60000000
|
||||
#define SIBA_IDLOW_SSBREV_27 0x70000000
|
||||
#define SIBA_IDHIGH 0x0ffc
|
||||
#define SIBA_IDHIGH_CORECODEMASK 0x00008FF0 /* Core Code */
|
||||
#define SIBA_IDHIGH_CORECODE_SHIFT 4
|
||||
#define SIBA_IDHIGH_CORECODE(id) \
|
||||
((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT)
|
||||
/* Revision Code (low part) */
|
||||
#define SIBA_IDHIGH_REVLO 0x0000000f
|
||||
/* Revision Code (high part) */
|
||||
#define SIBA_IDHIGH_REVHI 0x00007000
|
||||
#define SIBA_IDHIGH_REVHI_SHIFT 8
|
||||
#define SIBA_IDHIGH_REV(id) \
|
||||
((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \
|
||||
SIBA_IDHIGH_REVHI_SHIFT))
|
||||
#define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */
|
||||
#define SIBA_IDHIGH_VENDOR_SHIFT 16
|
||||
#define SIBA_IDHIGH_VENDOR(id) \
|
||||
((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT)
|
||||
|
||||
#define SIBA_SPROMSIZE_R123 64
|
||||
#define SIBA_SPROMSIZE_R4 220
|
||||
#define SIBA_SPROM_BASE 0x1000
|
||||
#define SIBA_SPROM_REV_CRC 0xff00
|
||||
#define SIBA_SPROM1_MAC_80211BG 0x1048
|
||||
#define SIBA_SPROM1_MAC_ETH 0x104e
|
||||
#define SIBA_SPROM1_MAC_80211A 0x1054
|
||||
#define SIBA_SPROM1_ETHPHY 0x105a
|
||||
#define SIBA_SPROM1_ETHPHY_MII_ETH0 0x001f
|
||||
#define SIBA_SPROM1_ETHPHY_MII_ETH1 0x03e0
|
||||
#define SIBA_SPROM1_ETHPHY_MDIO_ETH0 (1 << 14)
|
||||
#define SIBA_SPROM1_ETHPHY_MDIO_ETH1 (1 << 15)
|
||||
#define SIBA_SPROM1_BOARDINFO 0x105c
|
||||
#define SIBA_SPROM1_BOARDINFO_BREV 0x00ff
|
||||
#define SIBA_SPROM1_BOARDINFO_CCODE 0x0f00
|
||||
#define SIBA_SPROM1_BOARDINFO_ANTBG 0x3000
|
||||
#define SIBA_SPROM1_BOARDINFO_ANTA 0xc000
|
||||
#define SIBA_SPROM1_PA0B0 0x105e
|
||||
#define SIBA_SPROM1_PA0B1 0x1060
|
||||
#define SIBA_SPROM1_PA0B2 0x1062
|
||||
#define SIBA_SPROM1_GPIOA 0x1064
|
||||
#define SIBA_SPROM1_GPIOA_P0 0x00ff
|
||||
#define SIBA_SPROM1_GPIOA_P1 0xff00
|
||||
#define SIBA_SPROM1_GPIOB 0x1066
|
||||
#define SIBA_SPROM1_GPIOB_P2 0x00ff
|
||||
#define SIBA_SPROM1_GPIOB_P3 0xff00
|
||||
#define SIBA_SPROM1_MAXPWR 0x1068
|
||||
#define SIBA_SPROM1_MAXPWR_BG 0x00ff
|
||||
#define SIBA_SPROM1_MAXPWR_A 0xff00
|
||||
#define SIBA_SPROM1_PA1B0 0x106a
|
||||
#define SIBA_SPROM1_PA1B1 0x106c
|
||||
#define SIBA_SPROM1_PA1B2 0x106e
|
||||
#define SIBA_SPROM1_TSSI 0x1070
|
||||
#define SIBA_SPROM1_TSSI_BG 0x00ff
|
||||
#define SIBA_SPROM1_TSSI_A 0xff00
|
||||
#define SIBA_SPROM1_BFLOW 0x1072
|
||||
#define SIBA_SPROM1_AGAIN 0x1074
|
||||
#define SIBA_SPROM1_AGAIN_BG 0x00ff
|
||||
#define SIBA_SPROM1_AGAIN_A 0xff00
|
||||
#define SIBA_SPROM2_BFHIGH 0x1038
|
||||
#define SIBA_SPROM3_MAC_80211BG 0x104a
|
||||
#define SIBA_SPROM4_MAC_80211BG 0x104c
|
||||
#define SIBA_SPROM4_ETHPHY 0x105a
|
||||
#define SIBA_SPROM4_ETHPHY_ET0A 0x001f
|
||||
#define SIBA_SPROM4_ETHPHY_ET1A 0x03e0
|
||||
#define SIBA_SPROM4_CCODE 0x1052
|
||||
#define SIBA_SPROM4_ANTAVAIL 0x105d
|
||||
#define SIBA_SPROM4_ANTAVAIL_A 0x00ff
|
||||
#define SIBA_SPROM4_ANTAVAIL_BG 0xff00
|
||||
#define SIBA_SPROM4_BFLOW 0x1044
|
||||
#define SIBA_SPROM4_AGAIN01 0x105e
|
||||
#define SIBA_SPROM4_AGAIN0 0x00ff
|
||||
#define SIBA_SPROM4_AGAIN1 0xff00
|
||||
#define SIBA_SPROM4_AGAIN23 0x1060
|
||||
#define SIBA_SPROM4_AGAIN2 0x00ff
|
||||
#define SIBA_SPROM4_AGAIN3 0xff00
|
||||
#define SIBA_SPROM4_BFHIGH 0x1046
|
||||
#define SIBA_SPROM4_MAXP_BG 0x1080
|
||||
#define SIBA_SPROM4_MAXP_BG_MASK 0x00ff
|
||||
#define SIBA_SPROM4_TSSI_BG 0xff00
|
||||
#define SIBA_SPROM4_MAXP_A 0x108a
|
||||
#define SIBA_SPROM4_MAXP_A_MASK 0x00ff
|
||||
#define SIBA_SPROM4_TSSI_A 0xff00
|
||||
#define SIBA_SPROM4_GPIOA 0x1056
|
||||
#define SIBA_SPROM4_GPIOA_P0 0x00ff
|
||||
#define SIBA_SPROM4_GPIOA_P1 0xff00
|
||||
#define SIBA_SPROM4_GPIOB 0x1058
|
||||
#define SIBA_SPROM4_GPIOB_P2 0x00ff
|
||||
#define SIBA_SPROM4_GPIOB_P3 0xff00
|
||||
#define SIBA_SPROM5_BFLOW 0x104a
|
||||
#define SIBA_SPROM5_BFHIGH 0x104c
|
||||
#define SIBA_SPROM5_MAC_80211BG 0x1052
|
||||
#define SIBA_SPROM5_CCODE 0x1044
|
||||
#define SIBA_SPROM5_GPIOA 0x1076
|
||||
#define SIBA_SPROM5_GPIOA_P0 0x00ff
|
||||
#define SIBA_SPROM5_GPIOA_P1 0xff00
|
||||
#define SIBA_SPROM5_GPIOB 0x1078
|
||||
#define SIBA_SPROM5_GPIOB_P2 0x00ff
|
||||
#define SIBA_SPROM5_GPIOB_P3 0xff00
|
||||
#define SIBA_SPROM8_BFLOW 0x1084
|
||||
#define SIBA_SPROM8_BFHIGH 0x1086
|
||||
#define SIBA_SPROM8_CCODE 0x1092
|
||||
#define SIBA_SPROM8_ANTAVAIL 0x109c
|
||||
#define SIBA_SPROM8_ANTAVAIL_A 0xff00
|
||||
#define SIBA_SPROM8_ANTAVAIL_BG 0x00ff
|
||||
#define SIBA_SPROM8_AGAIN01 0x109e
|
||||
#define SIBA_SPROM8_AGAIN0 0x00ff
|
||||
#define SIBA_SPROM8_AGAIN1 0xff00
|
||||
#define SIBA_SPROM8_AGAIN23 0x10a0
|
||||
#define SIBA_SPROM8_AGAIN2 0x00ff
|
||||
#define SIBA_SPROM8_AGAIN3 0xff00
|
||||
#define SIBA_SPROM8_GPIOA 0x1096
|
||||
#define SIBA_SPROM8_GPIOA_P0 0x00ff
|
||||
#define SIBA_SPROM8_GPIOA_P1 0xff00
|
||||
#define SIBA_SPROM8_GPIOB 0x1098
|
||||
#define SIBA_SPROM8_GPIOB_P2 0x00ff
|
||||
#define SIBA_SPROM8_GPIOB_P3 0xff00
|
||||
#define SIBA_SPROM8_MAXP_BG 0x10c0
|
||||
#define SIBA_SPROM8_MAXP_BG_MASK 0x00ff
|
||||
#define SIBA_SPROM8_TSSI_BG 0xff00
|
||||
#define SIBA_SPROM8_MAXP_A 0x10c8
|
||||
#define SIBA_SPROM8_MAXP_A_MASK 0x00ff
|
||||
#define SIBA_SPROM8_TSSI_A 0xff00
|
||||
|
||||
#define SIBA_BOARDVENDOR_DELL 0x1028
|
||||
#define SIBA_BOARDVENDOR_BCM 0x14e4
|
||||
#define SIBA_BOARD_BCM4309G 0x0421
|
||||
#define SIBA_BOARD_MP4318 0x044a
|
||||
#define SIBA_BOARD_BU4306 0x0416
|
||||
#define SIBA_BOARD_BU4309 0x040a
|
||||
|
||||
#define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR
|
||||
#define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA
|
||||
#define SIBA_PCICORE_SBTOPCI0 0x0100
|
||||
#define SIBA_PCICORE_SBTOPCI1 0x0104
|
||||
#define SIBA_PCICORE_SBTOPCI2 0x0108
|
||||
#define SIBA_PCICORE_MDIO_CTL 0x0128
|
||||
#define SIBA_PCICORE_MDIO_DATA 0x012c
|
||||
#define SIBA_PCICORE_SBTOPCI_PREF 0x00000004
|
||||
#define SIBA_PCICORE_SBTOPCI_BURST 0x00000008
|
||||
#define SIBA_PCICORE_SBTOPCI_MRM 0x00000020
|
||||
|
||||
#endif /* _SIBA_SIBAREG_H_ */
|
||||
|
||||
@ -31,46 +31,8 @@
|
||||
|
||||
#include <sys/rman.h>
|
||||
|
||||
struct siba_softc {
|
||||
device_t sc_dev; /* Device ID */
|
||||
struct resource *sc_mem; /* Memory window on nexus */
|
||||
|
||||
bus_space_tag_t sc_bt;
|
||||
bus_space_handle_t sc_bh;
|
||||
bus_addr_t sc_maddr;
|
||||
bus_size_t sc_msize;
|
||||
|
||||
uint8_t sc_ncores;
|
||||
};
|
||||
|
||||
struct siba_devinfo {
|
||||
struct resource_list sdi_rl;
|
||||
/*devhandle_t sdi_devhandle; XXX*/
|
||||
/*struct rman sdi_intr_rman;*/
|
||||
|
||||
/* Accessors are needed for ivars below. */
|
||||
uint16_t sdi_vid;
|
||||
uint16_t sdi_devid;
|
||||
uint8_t sdi_rev;
|
||||
uint8_t sdi_idx; /* core index on bus */
|
||||
uint8_t sdi_irq; /* TODO */
|
||||
};
|
||||
|
||||
#define siba_read_2(sc, core, reg) \
|
||||
bus_space_read_2((sc)->sc_bt, (sc)->sc_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg))
|
||||
|
||||
#define siba_read_4(sc, core, reg) \
|
||||
bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg))
|
||||
|
||||
#define siba_write_2(sc, core, reg, val) \
|
||||
bus_space_write_2((sc)->sc_bt, (sc)->sc_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg), (val))
|
||||
|
||||
#define siba_write_4(sc, core, reg, val) \
|
||||
bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg), (val))
|
||||
struct siba_softc;
|
||||
struct siba_dev_softc;
|
||||
|
||||
enum siba_device_ivars {
|
||||
SIBA_IVAR_VENDOR,
|
||||
@ -89,4 +51,321 @@ SIBA_ACCESSOR(core_index, CORE_INDEX, uint8_t)
|
||||
|
||||
#undef SIBA_ACCESSOR
|
||||
|
||||
/* XXX just for SPROM1? */
|
||||
enum {
|
||||
SIBA_CCODE_WORLD,
|
||||
SIBA_CCODE_THAILAND,
|
||||
SIBA_CCODE_ISRAEL,
|
||||
SIBA_CCODE_JORDAN,
|
||||
SIBA_CCODE_CHINA,
|
||||
SIBA_CCODE_JAPAN,
|
||||
SIBA_CCODE_USA_CANADA_ANZ,
|
||||
SIBA_CCODE_EUROPE,
|
||||
SIBA_CCODE_USA_LOW,
|
||||
SIBA_CCODE_JAPAN_HIGH,
|
||||
SIBA_CCODE_ALL,
|
||||
SIBA_CCODE_NONE,
|
||||
};
|
||||
|
||||
#define siba_mips_read_2(sc, core, reg) \
|
||||
bus_space_read_2((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg))
|
||||
|
||||
#define siba_mips_read_4(sc, core, reg) \
|
||||
bus_space_read_4((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg))
|
||||
|
||||
#define siba_mips_write_2(sc, core, reg, val) \
|
||||
bus_space_write_2((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg), (val))
|
||||
|
||||
#define siba_mips_write_4(sc, core, reg, val) \
|
||||
bus_space_write_4((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
|
||||
(core * SIBA_CORE_LEN) + (reg), (val))
|
||||
|
||||
#define SIBA_READ_4(siba, reg) \
|
||||
bus_space_read_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
|
||||
#define SIBA_READ_2(siba, reg) \
|
||||
bus_space_read_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
|
||||
#define SIBA_READ_MULTI_1(siba, reg, addr, count) \
|
||||
bus_space_read_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
|
||||
(reg), (addr), (count))
|
||||
#define SIBA_READ_MULTI_2(siba, reg, addr, count) \
|
||||
bus_space_read_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
|
||||
(reg), (addr), (count))
|
||||
#define SIBA_READ_MULTI_4(siba, reg, addr, count) \
|
||||
bus_space_read_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
|
||||
(reg), (addr), (count))
|
||||
|
||||
#define SIBA_WRITE_4(siba, reg, val) \
|
||||
bus_space_write_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, \
|
||||
(reg), (val))
|
||||
#define SIBA_WRITE_2(siba, reg, val) \
|
||||
bus_space_write_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, \
|
||||
(reg), (val))
|
||||
#define SIBA_WRITE_MULTI_1(siba, reg, addr, count) \
|
||||
bus_space_write_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
|
||||
(reg), (addr), (count))
|
||||
#define SIBA_WRITE_MULTI_2(siba, reg, addr, count) \
|
||||
bus_space_write_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
|
||||
(reg), (addr), (count))
|
||||
#define SIBA_WRITE_MULTI_4(siba, reg, addr, count) \
|
||||
bus_space_write_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
|
||||
(reg), (addr), (count))
|
||||
|
||||
#define SIBA_BARRIER(siba, flags) \
|
||||
bus_space_barrier((siba)->siba_mem_bt, (siba)->siba_mem_bh, (0),\
|
||||
(0), (flags))
|
||||
|
||||
#define SIBA_SETBITS_4(siba, reg, bits) \
|
||||
SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) | (bits))
|
||||
#define SIBA_SETBITS_2(siba, reg, bits) \
|
||||
SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) | (bits))
|
||||
|
||||
#define SIBA_FILT_SETBITS_4(siba, reg, filt, bits) \
|
||||
SIBA_WRITE_4((siba), (reg), (SIBA_READ_4((siba), \
|
||||
(reg)) & (filt)) | (bits))
|
||||
#define SIBA_FILT_SETBITS_2(siba, reg, filt, bits) \
|
||||
SIBA_WRITE_2((siba), (reg), (SIBA_READ_2((siba), \
|
||||
(reg)) & (filt)) | (bits))
|
||||
|
||||
#define SIBA_CLRBITS_4(siba, reg, bits) \
|
||||
SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) & ~(bits))
|
||||
#define SIBA_CLRBITS_2(siba, reg, bits) \
|
||||
SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) & ~(bits))
|
||||
|
||||
#define SIBA_CC_READ32(scc, offset) \
|
||||
siba_read_4((scc)->scc_dev, offset)
|
||||
#define SIBA_CC_WRITE32(scc, offset, val) \
|
||||
siba_write_4((scc)->scc_dev, offset, val)
|
||||
#define SIBA_CC_MASK32(scc, offset, mask) \
|
||||
SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) & (mask))
|
||||
#define SIBA_CC_SET32(scc, offset, set) \
|
||||
SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) | (set))
|
||||
#define SIBA_CC_MASKSET32(scc, offset, mask, set) \
|
||||
SIBA_CC_WRITE32(scc, offset, \
|
||||
(SIBA_CC_READ32(scc, offset) & (mask)) | (set))
|
||||
|
||||
enum siba_type {
|
||||
SIBA_TYPE_SSB,
|
||||
SIBA_TYPE_PCI,
|
||||
SIBA_TYPE_PCMCIA,
|
||||
};
|
||||
|
||||
enum siba_clock {
|
||||
SIBA_CLOCK_DYNAMIC,
|
||||
SIBA_CLOCK_SLOW,
|
||||
SIBA_CLOCK_FAST,
|
||||
};
|
||||
|
||||
enum siba_clksrc {
|
||||
SIBA_CC_CLKSRC_PCI,
|
||||
SIBA_CC_CLKSRC_CRYSTAL,
|
||||
SIBA_CC_CLKSRC_LOWPW,
|
||||
};
|
||||
|
||||
struct siba_cc_pmu0_plltab {
|
||||
uint16_t freq; /* in kHz.*/
|
||||
uint8_t xf; /* crystal frequency */
|
||||
uint8_t wb_int;
|
||||
uint32_t wb_frac;
|
||||
};
|
||||
|
||||
struct siba_cc_pmu1_plltab {
|
||||
uint16_t freq;
|
||||
uint8_t xf;
|
||||
uint8_t p1div;
|
||||
uint8_t p2div;
|
||||
uint8_t ndiv_int;
|
||||
uint32_t ndiv_frac;
|
||||
};
|
||||
|
||||
struct siba_cc_pmu_res_updown {
|
||||
uint8_t res;
|
||||
uint16_t updown;
|
||||
};
|
||||
|
||||
#define SIBA_CC_PMU_DEP_SET 1
|
||||
#define SIBA_CC_PMU_DEP_ADD 2
|
||||
#define SIBA_CC_PMU_DEP_REMOVE 3
|
||||
|
||||
struct siba_cc_pmu_res_depend {
|
||||
uint8_t res;
|
||||
uint8_t task;
|
||||
uint32_t depend;
|
||||
};
|
||||
|
||||
struct siba_sprom {
|
||||
uint8_t rev; /* revision */
|
||||
uint8_t mac_80211bg[6]; /* address for 802.11b/g */
|
||||
uint8_t mac_eth[6]; /* address for Ethernet */
|
||||
uint8_t mac_80211a[6]; /* address for 802.11a */
|
||||
uint8_t mii_eth0; /* MII address for eth0 */
|
||||
uint8_t mii_eth1; /* MII address for eth1 */
|
||||
uint8_t mdio_eth0; /* MDIO for eth0 */
|
||||
uint8_t mdio_eth1; /* MDIO for eth1 */
|
||||
uint8_t brev; /* board revision */
|
||||
uint8_t ccode; /* Country Code */
|
||||
uint8_t ant_a; /* A-PHY antenna */
|
||||
uint8_t ant_bg; /* B/G-PHY antenna */
|
||||
uint16_t pa0b0;
|
||||
uint16_t pa0b1;
|
||||
uint16_t pa0b2;
|
||||
uint16_t pa1b0;
|
||||
uint16_t pa1b1;
|
||||
uint16_t pa1b2;
|
||||
uint8_t gpio0;
|
||||
uint8_t gpio1;
|
||||
uint8_t gpio2;
|
||||
uint8_t gpio3;
|
||||
uint16_t maxpwr_a; /* A-PHY Max Power */
|
||||
uint16_t maxpwr_bg; /* BG-PHY Max Power */
|
||||
uint8_t tssi_a; /* Idle TSSI */
|
||||
uint8_t tssi_bg; /* Idle TSSI */
|
||||
uint16_t bf_lo; /* boardflags */
|
||||
uint16_t bf_hi; /* boardflags */
|
||||
struct {
|
||||
struct {
|
||||
int8_t a0, a1, a2, a3;
|
||||
} ghz24;
|
||||
struct {
|
||||
int8_t a0, a1, a2, a3;
|
||||
} ghz5;
|
||||
} again; /* antenna gain */
|
||||
};
|
||||
|
||||
struct siba_cc_pmu {
|
||||
uint8_t rev; /* PMU rev */
|
||||
uint32_t freq; /* crystal freq in kHz */
|
||||
};
|
||||
|
||||
struct siba_cc {
|
||||
struct siba_dev_softc *scc_dev;
|
||||
uint32_t scc_caps;
|
||||
struct siba_cc_pmu scc_pmu;
|
||||
uint16_t scc_powerup_delay;
|
||||
};
|
||||
|
||||
struct siba_pci {
|
||||
struct siba_dev_softc *spc_dev;
|
||||
uint8_t spc_inited;
|
||||
uint8_t spc_hostmode;
|
||||
};
|
||||
|
||||
struct siba_bus_ops {
|
||||
uint16_t (*read_2)(struct siba_dev_softc *,
|
||||
uint16_t);
|
||||
uint32_t (*read_4)(struct siba_dev_softc *,
|
||||
uint16_t);
|
||||
void (*write_2)(struct siba_dev_softc *,
|
||||
uint16_t, uint16_t);
|
||||
void (*write_4)(struct siba_dev_softc *,
|
||||
uint16_t, uint32_t);
|
||||
void (*read_multi_1)(struct siba_dev_softc *,
|
||||
void *, size_t, uint16_t);
|
||||
void (*read_multi_2)(struct siba_dev_softc *,
|
||||
void *, size_t, uint16_t);
|
||||
void (*read_multi_4)(struct siba_dev_softc *,
|
||||
void *, size_t, uint16_t);
|
||||
void (*write_multi_1)(struct siba_dev_softc *,
|
||||
const void *, size_t, uint16_t);
|
||||
void (*write_multi_2)(struct siba_dev_softc *,
|
||||
const void *, size_t, uint16_t);
|
||||
void (*write_multi_4)(struct siba_dev_softc *,
|
||||
const void *, size_t, uint16_t);
|
||||
};
|
||||
|
||||
struct siba_dev_softc {
|
||||
struct siba_softc *sd_bus;
|
||||
struct siba_devid sd_id;
|
||||
const struct siba_bus_ops *sd_ops;
|
||||
|
||||
uint8_t sd_coreidx;
|
||||
};
|
||||
|
||||
struct siba_devinfo {
|
||||
struct resource_list sdi_rl;
|
||||
/*devhandle_t sdi_devhandle; XXX*/
|
||||
/*struct rman sdi_intr_rman;*/
|
||||
|
||||
/* Accessors are needed for ivars below. */
|
||||
uint16_t sdi_vid;
|
||||
uint16_t sdi_devid;
|
||||
uint8_t sdi_rev;
|
||||
uint8_t sdi_idx; /* core index on bus */
|
||||
uint8_t sdi_irq; /* TODO */
|
||||
};
|
||||
|
||||
struct siba_softc {
|
||||
/*
|
||||
* common variables which used for siba(4) bus and siba_bwn bridge.
|
||||
*/
|
||||
device_t siba_dev; /* Device ID */
|
||||
struct resource *siba_mem_res;
|
||||
bus_space_tag_t siba_mem_bt;
|
||||
bus_space_handle_t siba_mem_bh;
|
||||
bus_addr_t siba_maddr;
|
||||
bus_size_t siba_msize;
|
||||
uint8_t siba_ncores;
|
||||
|
||||
/*
|
||||
* the following variables are only used for siba_bwn bridge.
|
||||
*/
|
||||
|
||||
enum siba_type siba_type;
|
||||
int siba_invalid;
|
||||
|
||||
struct siba_dev_softc *siba_curdev; /* only for PCI */
|
||||
struct siba_dev_softc siba_devs[SIBA_MAX_CORES];
|
||||
int siba_ndevs;
|
||||
|
||||
uint16_t siba_pci_vid;
|
||||
uint16_t siba_pci_did;
|
||||
uint16_t siba_pci_subvid;
|
||||
uint16_t siba_pci_subdid;
|
||||
int siba_mem_rid;
|
||||
|
||||
uint16_t siba_chipid; /* for CORE 0 */
|
||||
uint16_t siba_chiprev;
|
||||
uint8_t siba_chippkg;
|
||||
|
||||
struct siba_cc siba_cc; /* ChipCommon */
|
||||
struct siba_pci siba_pci; /* PCI-core */
|
||||
const struct siba_bus_ops *siba_ops;
|
||||
|
||||
/* board informations */
|
||||
uint16_t siba_board_vendor;
|
||||
uint16_t siba_board_type;
|
||||
uint16_t siba_board_rev;
|
||||
struct siba_sprom siba_sprom; /* SPROM */
|
||||
uint16_t siba_spromsize; /* in word size */
|
||||
};
|
||||
|
||||
void siba_powerup(struct siba_softc *, int);
|
||||
uint16_t siba_read_2(struct siba_dev_softc *, uint16_t);
|
||||
void siba_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
|
||||
uint32_t siba_read_4(struct siba_dev_softc *, uint16_t);
|
||||
void siba_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
|
||||
void siba_dev_up(struct siba_dev_softc *, uint32_t);
|
||||
void siba_dev_down(struct siba_dev_softc *, uint32_t);
|
||||
int siba_powerdown(struct siba_softc *);
|
||||
int siba_dev_isup(struct siba_dev_softc *);
|
||||
void siba_pcicore_intr(struct siba_pci *, struct siba_dev_softc *);
|
||||
uint32_t siba_dma_translation(struct siba_dev_softc *);
|
||||
void *siba_dma_alloc_consistent(struct siba_dev_softc *, size_t,
|
||||
bus_addr_t *);
|
||||
void siba_read_multi_1(struct siba_dev_softc *, void *, size_t,
|
||||
uint16_t);
|
||||
void siba_read_multi_2(struct siba_dev_softc *, void *, size_t,
|
||||
uint16_t);
|
||||
void siba_read_multi_4(struct siba_dev_softc *, void *, size_t,
|
||||
uint16_t);
|
||||
void siba_write_multi_1(struct siba_dev_softc *, const void *,
|
||||
size_t, uint16_t);
|
||||
void siba_write_multi_2(struct siba_dev_softc *, const void *,
|
||||
size_t, uint16_t);
|
||||
void siba_write_multi_4(struct siba_dev_softc *, const void *,
|
||||
size_t, uint16_t);
|
||||
void siba_barrier(struct siba_dev_softc *, int);
|
||||
|
||||
#endif /* _SIBA_SIBAVAR_H_ */
|
||||
|
||||
9
sys/modules/siba_bwn/Makefile
Normal file
9
sys/modules/siba_bwn/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/siba
|
||||
|
||||
KMOD= siba_bwn
|
||||
SRCS= siba_core.c siba_bwn.c sibareg.h sibavar.h
|
||||
SRCS+= device_if.h bus_if.h pci_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
x
Reference in New Issue
Block a user