Add et(4), a port of DragonFly's Agere ET1310 10/100/Gigabit

Ethernet device driver, written by sephe@

Obtained from:	DragonFly
Sponsored by:	iXsystems
MFC after:	2 weeks

sys/amd64/conf/GENERIC

@@ -204,6 +204,7 @@ device		bce		# Broadcom BCM5706/BCM5708 Gigabit Ethernet
 device		bfe		# Broadcom BCM440x 10/100 Ethernet
 device		bge		# Broadcom BCM570xx Gigabit Ethernet
 device		dc		# DEC/Intel 21143 and various workalikes
+device		et		# Agere ET1310 10/100/Gigabit Ethernet
 device		fxp		# Intel EtherExpress PRO/100B (82557, 82558)
 device		jme		# JMicron JMC250 Gigabit/JMC260 Fast Ethernet
 device		lge		# Level 1 LXT1001 gigabit Ethernet

sys/conf/NOTES

@@ -1876,6 +1876,7 @@ device		bge		# Broadcom BCM570xx Gigabit Ethernet
 device		cxgb		# Chelsio T3 10 Gigabit Ethernet
 device		cxgb_t3fw	# Chelsio T3 10 Gigabit Ethernet firmware
 device		dc		# DEC/Intel 21143 and various workalikes
+device		et		# Agere ET1310 10/100/Gigabit Ethernet
 device		fxp		# Intel EtherExpress PRO/100B (82557, 82558)
 hint.fxp.0.prefer_iomap="0"
 device		gem		# Apple GMAC/Sun ERI/Sun GEM

sys/conf/files

@@ -636,6 +636,7 @@ dev/em/e1000_phy.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/em"
 dev/em/e1000_osdep.c		optional em | igb \
 	compile-with "${NORMAL_C} -I$S/dev/em"
+dev/et/if_et.c			optional et
 dev/en/if_en_pci.c		optional en pci
 dev/en/midway.c			optional en
 dev/ep/if_ep.c			optional ep
@@ -904,6 +905,7 @@ dev/mii/ruephy.c		optional miibus | ruephy
 dev/mii/smcphy.c		optional miibus | smcphy
 dev/mii/tdkphy.c		optional miibus | tdkphy
 dev/mii/tlphy.c			optional miibus | tlphy
+dev/mii/truephy.c		optional miibus | truephy
 dev/mii/ukphy.c			optional miibus | mii
 dev/mii/ukphy_subr.c		optional miibus | mii
 dev/mii/xmphy.c			optional miibus | xmphy

sys/dev/et/if_etreg.h

@@ -0,0 +1,436 @@
+/*-
+ * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
+ * 
+ * This code is derived from software contributed to The DragonFly Project
+ * by Sepherosa Ziehau <sepherosa@gmail.com>
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of The DragonFly Project nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific, prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * 
+ * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.3 2007/10/23 14:28:42 sephe Exp $
+ * $FreeBSD$
+ */
+/*-
+ * Portions of this code is derived from NetBSD which is covered by
+ * the following license:
+ *
+ * Copyright (c) 2004, 2005 David Young.  All rights reserved.
+ *
+ * Programmed for NetBSD by David Young.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of David Young may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
+ * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * $DragonFly: src/sys/sys/bitops.h,v 1.1 2007/10/14 04:15:17 sephe Exp $
+ */
+
+#ifndef _IF_ETREG_H
+#define _IF_ETREG_H
+
+/*
+ * __BIT(n): Return a bitmask with bit n set, where the least
+ *           significant bit is bit 0.
+ *
+ * __BITS(m, n): Return a bitmask with bits m through n, inclusive,
+ *               set.  It does not matter whether m>n or m<=n.  The
+ *               least significant bit is bit 0.
+ *
+ * A "bitfield" is a span of consecutive bits defined by a bitmask,
+ * where 1s select the bits in the bitfield.  __SHIFTIN, __SHIFTOUT,
+ * and __SHIFTOUT_MASK help read and write bitfields from device
+ * registers.
+ *
+ * __SHIFTIN(v, mask): Left-shift bits `v' into the bitfield
+ *                     defined by `mask', and return them.  No
+ *                     side-effects.
+ *
+ * __SHIFTOUT(v, mask): Extract and return the bitfield selected
+ *                      by `mask' from `v', right-shifting the
+ *                      bits so that the rightmost selected bit
+ *                      is at bit 0.  No side-effects.
+ *
+ * __SHIFTOUT_MASK(mask): Right-shift the bits in `mask' so that
+ *                        the rightmost non-zero bit is at bit
+ *                        0.  This is useful for finding the
+ *                        greatest unsigned value that a bitfield
+ *                        can hold.  No side-effects.  Note that
+ *                        __SHIFTOUT_MASK(m) = __SHIFTOUT(m, m).
+ */
+
+/* __BIT(n): nth bit, where __BIT(0) == 0x1. */
+#define	__BIT(__n) (((__n) == 32) ? 0 : ((uint32_t)1 << (__n)))
+
+/* __BITS(m, n): bits m through n, m < n. */
+#define	__BITS(__m, __n)	\
+	((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
+
+/* Find least significant bit that is set */
+#define	__LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
+
+#define	__SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask))
+#define	__SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask))
+#define	__SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask))
+
+#define ET_MEM_TXSIZE_EX		182
+#define ET_MEM_RXSIZE_MIN		608
+#define ET_MEM_RXSIZE_DEFAULT		11216
+#define ET_MEM_SIZE			16384
+#define ET_MEM_UNIT			16
+
+/*
+ * PCI registers
+ *
+ * ET_PCIV_ACK_LATENCY_{128,256} are from
+ * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5
+ *
+ * ET_PCIV_REPLAY_TIMER_{128,256} are from
+ * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4
+ */
+#define ET_PCIR_BAR			PCIR_BAR(0)
+
+#define ET_PCIR_DEVICE_CAPS		0x4c
+#define ET_PCIM_DEVICE_CAPS_MAX_PLSZ	0x7	/* Max playload size */
+#define ET_PCIV_DEVICE_CAPS_PLSZ_128	0x0
+#define ET_PCIV_DEVICE_CAPS_PLSZ_256	0x1
+
+#define ET_PCIR_DEVICE_CTRL		0x50
+#define ET_PCIM_DEVICE_CTRL_MAX_RRSZ	0x7000	/* Max read request size */
+#define ET_PCIV_DEVICE_CTRL_RRSZ_2K	0x4000
+
+#define ET_PCIR_MAC_ADDR0		0xa4
+#define ET_PCIR_MAC_ADDR1		0xa8
+
+#define ET_PCIR_EEPROM_STATUS		0xb2	/* XXX undocumented */
+#define ET_PCIM_EEPROM_STATUS_ERROR	0x4c
+
+#define ET_PCIR_ACK_LATENCY		0xc0
+#define ET_PCIV_ACK_LATENCY_128		237
+#define ET_PCIV_ACK_LATENCY_256		416
+
+#define ET_PCIR_REPLAY_TIMER		0xc2
+#define ET_REPLAY_TIMER_RX_L0S_ADJ	250	/* XXX infered from default */
+#define ET_PCIV_REPLAY_TIMER_128	(711 + ET_REPLAY_TIMER_RX_L0S_ADJ)
+#define ET_PCIV_REPLAY_TIMER_256	(1248 + ET_REPLAY_TIMER_RX_L0S_ADJ)
+
+#define ET_PCIR_L0S_L1_LATENCY		0xcf
+#define ET_PCIM_L0S_LATENCY		__BITS(2, 0)
+#define ET_PCIM_L1_LATENCY		__BITS(5, 3)
+#define ET_PCIV_L0S_LATENCY(l)		__SHIFTIN((l) - 1, ET_PCIM_L0S_LATENCY)
+#define ET_PCIV_L1_LATENCY(l)		__SHIFTIN((l) - 1, ET_PCIM_L1_LATENCY)
+
+/*
+ * CSR
+ */
+#define ET_TXQUEUE_START		0x0000
+#define ET_TXQUEUE_END			0x0004
+#define ET_RXQUEUE_START		0x0008
+#define ET_RXQUEUE_END			0x000c
+#define ET_QUEUE_ADDR(addr)		(((addr) / ET_MEM_UNIT) - 1)
+#define ET_QUEUE_ADDR_START		0
+#define ET_QUEUE_ADDR_END		ET_QUEUE_ADDR(ET_MEM_SIZE)
+
+#define ET_PM				0x0010
+#define ET_PM_SYSCLK_GATE		__BIT(3)
+#define ET_PM_TXCLK_GATE		__BIT(4)
+#define ET_PM_RXCLK_GATE		__BIT(5)
+
+#define ET_INTR_STATUS			0x0018
+#define ET_INTR_MASK			0x001c
+
+#define ET_SWRST			0x0028
+#define ET_SWRST_TXDMA			__BIT(0)
+#define ET_SWRST_RXDMA			__BIT(1)
+#define ET_SWRST_TXMAC			__BIT(2)
+#define ET_SWRST_RXMAC			__BIT(3)
+#define ET_SWRST_MAC			__BIT(4)
+#define ET_SWRST_MAC_STAT		__BIT(5)
+#define ET_SWRST_MMC			__BIT(6)
+#define ET_SWRST_SELFCLR_DISABLE	__BIT(31)
+
+#define ET_MSI_CFG			0x0030
+
+#define ET_LOOPBACK			0x0034
+
+#define ET_TIMER			0x0038
+
+#define ET_TXDMA_CTRL			0x1000
+#define ET_TXDMA_CTRL_HALT		__BIT(0)
+#define ET_TXDMA_CTRL_CACHE_THR		__BITS(7, 4)
+#define ET_TXDMA_CTRL_SINGLE_EPKT	__BIT(8)	/* ??? */
+
+#define ET_TX_RING_HI			0x1004
+#define ET_TX_RING_LO			0x1008
+#define ET_TX_RING_CNT			0x100c
+
+#define ET_TX_STATUS_HI			0x101c
+#define ET_TX_STATUS_LO			0x1020
+
+#define ET_TX_READY_POS			0x1024
+#define ET_TX_READY_POS_INDEX		__BITS(9, 0)
+#define ET_TX_READY_POS_WRAP		__BIT(10)
+
+#define ET_TX_DONE_POS			0x1060
+#define ET_TX_DONE_POS_INDEX		__BITS(9, 0)
+#define ET_TX_DONE_POS_WRAP		__BIT(10)
+
+#define ET_RXDMA_CTRL			0x2000
+#define ET_RXDMA_CTRL_HALT		__BIT(0)
+#define ET_RXDMA_CTRL_RING0_SIZE	__BITS(9, 8)
+#define ET_RXDMA_CTRL_RING0_128		0		/* 127 */
+#define ET_RXDMA_CTRL_RING0_256		1		/* 255 */
+#define ET_RXDMA_CTRL_RING0_512		2		/* 511 */
+#define ET_RXDMA_CTRL_RING0_1024	3		/* 1023 */
+#define ET_RXDMA_CTRL_RING0_ENABLE	__BIT(10)
+#define ET_RXDMA_CTRL_RING1_SIZE	__BITS(12, 11)
+#define ET_RXDMA_CTRL_RING1_2048	0		/* 2047 */
+#define ET_RXDMA_CTRL_RING1_4096	1		/* 4095 */
+#define ET_RXDMA_CTRL_RING1_8192	2		/* 8191 */
+#define ET_RXDMA_CTRL_RING1_16384	3		/* 16383 (9022?) */
+#define ET_RXDMA_CTRL_RING1_ENABLE	__BIT(13)
+#define ET_RXDMA_CTRL_HALTED		__BIT(17)
+
+#define ET_RX_STATUS_LO			0x2004
+#define ET_RX_STATUS_HI			0x2008
+
+#define ET_RX_INTR_NPKTS		0x200c
+#define ET_RX_INTR_DELAY		0x2010
+
+#define ET_RXSTAT_LO			0x2020
+#define ET_RXSTAT_HI			0x2024
+#define ET_RXSTAT_CNT			0x2028
+
+#define ET_RXSTAT_POS			0x2030
+#define ET_RXSTAT_POS_INDEX		__BITS(11, 0)
+#define ET_RXSTAT_POS_WRAP		__BIT(12)
+
+#define ET_RXSTAT_MINCNT		0x2038
+
+#define ET_RX_RING0_LO			0x203c
+#define ET_RX_RING0_HI			0x2040
+#define ET_RX_RING0_CNT			0x2044
+
+#define ET_RX_RING0_POS			0x204c
+#define ET_RX_RING0_POS_INDEX		__BITS(9, 0)
+#define ET_RX_RING0_POS_WRAP		__BIT(10)
+
+#define ET_RX_RING0_MINCNT		0x2054
+
+#define ET_RX_RING1_LO			0x2058
+#define ET_RX_RING1_HI			0x205c
+#define ET_RX_RING1_CNT			0x2060
+
+#define ET_RX_RING1_POS			0x2068
+#define ET_RX_RING1_POS_INDEX		__BITS(9, 0)
+#define ET_RX_RING1_POS_WRAP		__BIT(10)
+
+#define ET_RX_RING1_MINCNT		0x2070
+
+#define ET_TXMAC_CTRL			0x3000
+#define ET_TXMAC_CTRL_ENABLE		__BIT(0)
+#define ET_TXMAC_CTRL_FC_DISABLE	__BIT(3)
+
+#define ET_TXMAC_FLOWCTRL		0x3010
+
+#define ET_RXMAC_CTRL			0x4000
+#define ET_RXMAC_CTRL_ENABLE		__BIT(0)
+#define ET_RXMAC_CTRL_NO_PKTFILT	__BIT(2)
+#define ET_RXMAC_CTRL_WOL_DISABLE	__BIT(3)
+
+#define ET_WOL_CRC			0x4004
+#define ET_WOL_SA_LO			0x4010
+#define ET_WOL_SA_HI			0x4014
+#define ET_WOL_MASK			0x4018
+
+#define ET_UCAST_FILTADDR1		0x4068
+#define ET_UCAST_FILTADDR2		0x406c
+#define ET_UCAST_FILTADDR3		0x4070
+
+#define ET_MULTI_HASH			0x4074
+
+#define ET_PKTFILT			0x4084
+#define ET_PKTFILT_BCAST		__BIT(0)
+#define ET_PKTFILT_MCAST		__BIT(1)
+#define ET_PKTFILT_UCAST		__BIT(2)
+#define ET_PKTFILT_FRAG			__BIT(3)
+#define ET_PKTFILT_MINLEN		__BITS(22, 16)
+
+#define ET_RXMAC_MC_SEGSZ		0x4088
+#define ET_RXMAC_MC_SEGSZ_ENABLE	__BIT(0)
+#define ET_RXMAC_MC_SEGSZ_FC		__BIT(1)
+#define ET_RXMAC_MC_SEGSZ_MAX		__BITS(9, 2)
+#define ET_RXMAC_SEGSZ(segsz)		((segsz) / ET_MEM_UNIT)
+#define ET_RXMAC_CUT_THRU_FRMLEN	8074
+
+#define ET_RXMAC_MC_WATERMARK		0x408c
+#define ET_RXMAC_SPACE_AVL		0x4094
+
+#define ET_RXMAC_MGT			0x4098
+#define ET_RXMAC_MGT_PASS_ECRC		__BIT(4)
+#define ET_RXMAC_MGT_PASS_ELEN		__BIT(5)
+#define ET_RXMAC_MGT_PASS_ETRUNC	__BIT(16)
+#define ET_RXMAC_MGT_CHECK_PKT		__BIT(17)
+
+#define ET_MAC_CFG1			0x5000
+#define ET_MAC_CFG1_TXEN		__BIT(0)
+#define ET_MAC_CFG1_SYNC_TXEN		__BIT(1)
+#define ET_MAC_CFG1_RXEN		__BIT(2)
+#define ET_MAC_CFG1_SYNC_RXEN		__BIT(3)
+#define ET_MAC_CFG1_TXFLOW		__BIT(4)
+#define ET_MAC_CFG1_RXFLOW		__BIT(5)
+#define ET_MAC_CFG1_LOOPBACK		__BIT(8)
+#define ET_MAC_CFG1_RST_TXFUNC		__BIT(16)
+#define ET_MAC_CFG1_RST_RXFUNC		__BIT(17)
+#define ET_MAC_CFG1_RST_TXMC		__BIT(18)
+#define ET_MAC_CFG1_RST_RXMC		__BIT(19)
+#define ET_MAC_CFG1_SIM_RST		__BIT(30)
+#define ET_MAC_CFG1_SOFT_RST		__BIT(31)
+
+#define ET_MAC_CFG2			0x5004
+#define ET_MAC_CFG2_FDX			__BIT(0)
+#define ET_MAC_CFG2_CRC			__BIT(1)
+#define ET_MAC_CFG2_PADCRC		__BIT(2)
+#define ET_MAC_CFG2_LENCHK		__BIT(4)
+#define ET_MAC_CFG2_BIGFRM		__BIT(5)
+#define ET_MAC_CFG2_MODE_MII		__BIT(8)
+#define ET_MAC_CFG2_MODE_GMII		__BIT(9)
+#define ET_MAC_CFG2_PREAMBLE_LEN	__BITS(15, 12)
+
+#define ET_IPG				0x5008
+#define ET_IPG_B2B			__BITS(6, 0)
+#define ET_IPG_MINIFG			__BITS(15, 8)
+#define ET_IPG_NONB2B_2			__BITS(22, 16)
+#define ET_IPG_NONB2B_1			__BITS(30, 24)
+
+#define ET_MAC_HDX			0x500c
+#define ET_MAC_HDX_COLLWIN		__BITS(9, 0)
+#define ET_MAC_HDX_REXMIT_MAX		__BITS(15, 12)
+#define ET_MAC_HDX_EXC_DEFER		__BIT(16)
+#define ET_MAC_HDX_NOBACKOFF		__BIT(17)
+#define ET_MAC_HDX_BP_NOBACKOFF		__BIT(18)
+#define ET_MAC_HDX_ALT_BEB		__BIT(19)
+#define ET_MAC_HDX_ALT_BEB_TRUNC	__BITS(23, 20)
+
+#define ET_MAX_FRMLEN			0x5010
+
+#define ET_MII_CFG			0x5020
+#define ET_MII_CFG_CLKRST		__BITS(2, 0)
+#define ET_MII_CFG_PREAMBLE_SUP		__BIT(4)
+#define ET_MII_CFG_SCAN_AUTOINC		__BIT(5)
+#define ET_MII_CFG_RST			__BIT(31)
+
+#define ET_MII_CMD			0x5024
+#define ET_MII_CMD_READ			__BIT(0)
+
+#define ET_MII_ADDR			0x5028
+#define ET_MII_ADDR_REG			__BITS(4, 0)
+#define ET_MII_ADDR_PHY			__BITS(12, 8)
+
+#define ET_MII_CTRL			0x502c
+#define ET_MII_CTRL_VALUE		__BITS(15, 0) 
+
+#define ET_MII_STAT			0x5030
+#define ET_MII_STAT_VALUE		__BITS(15, 0)
+
+#define ET_MII_IND			0x5034
+#define ET_MII_IND_BUSY			__BIT(0)
+#define ET_MII_IND_INVALID		__BIT(2)
+
+#define ET_MAC_CTRL			0x5038
+#define ET_MAC_CTRL_MODE_MII		__BIT(24)
+#define ET_MAC_CTRL_LHDX		__BIT(25)
+#define ET_MAC_CTRL_GHDX		__BIT(26)
+
+#define ET_MAC_ADDR1			0x5040
+#define ET_MAC_ADDR2			0x5044
+
+#define ET_MMC_CTRL			0x7000
+#define ET_MMC_CTRL_ENABLE		__BIT(0)
+#define ET_MMC_CTRL_ARB_DISABLE		__BIT(1)
+#define ET_MMC_CTRL_RXMAC_DISABLE	__BIT(2)
+#define ET_MMC_CTRL_TXMAC_DISABLE	__BIT(3)
+#define ET_MMC_CTRL_TXDMA_DISABLE	__BIT(4)
+#define ET_MMC_CTRL_RXDMA_DISABLE	__BIT(5)
+#define ET_MMC_CTRL_FORCE_CE		__BIT(6)
+
+/*
+ * Interrupts
+ */
+#define ET_INTR_TXEOF			__BIT(3)
+#define ET_INTR_TXDMA_ERROR		__BIT(4)
+#define ET_INTR_RXEOF			__BIT(5)
+#define ET_INTR_RXRING0_LOW		__BIT(6)
+#define ET_INTR_RXRING1_LOW		__BIT(7)
+#define ET_INTR_RXSTAT_LOW		__BIT(8)
+#define ET_INTR_RXDMA_ERROR		__BIT(9)
+#define ET_INTR_TIMER			__BIT(14)
+#define ET_INTR_WOL			__BIT(15)
+#define ET_INTR_PHY			__BIT(16)
+#define ET_INTR_TXMAC			__BIT(17)
+#define ET_INTR_RXMAC			__BIT(18)
+#define ET_INTR_MAC_STATS		__BIT(19)
+#define ET_INTR_SLAVE_TO		__BIT(20)
+
+#define ET_INTRS			(ET_INTR_TXEOF | \
+					 ET_INTR_RXEOF | \
+					 ET_INTR_TIMER)
+
+/*
+ * RX ring position uses same layout
+ */
+#define ET_RX_RING_POS_INDEX		__BITS(9, 0)
+#define ET_RX_RING_POS_WRAP		__BIT(10)
+
+/*
+ * PCI IDs
+ */
+#define PCI_VENDOR_LUCENT		0x11c1
+#define PCI_PRODUCT_LUCENT_ET1310	0xed00		/* ET1310 10/100/1000M Ethernet */
+#define PCI_PRODUCT_LUCENT_ET1310_FAST	0xed01		/* ET1310 10/100M Ethernet */
+
+#endif	/* !_IF_ETREG_H */

sys/dev/et/if_etvar.h

@@ -0,0 +1,279 @@
+/*-
+ * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
+ * 
+ * This code is derived from software contributed to The DragonFly Project
+ * by Sepherosa Ziehau <sepherosa@gmail.com>
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of The DragonFly Project nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific, prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * 
+ * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $
+ * $FreeBSD$
+ */
+
+#ifndef _IF_ETVAR_H
+#define _IF_ETVAR_H
+
+/* DragonFly compatibility */
+#define EVL_ENCAPLEN		ETHER_VLAN_ENCAP_LEN
+ 
+/*
+ * Allocate the right type of mbuf for the desired total length.
+ */
+static __inline struct mbuf *
+m_getl(int len, int how, int type, int flags, int *psize)
+{
+	struct mbuf *m;
+	int size;
+
+	if (len >= MINCLSIZE) {
+		m = m_getcl(how, type, flags);
+		size = MCLBYTES;
+	} else if (flags & M_PKTHDR) {
+		m = m_gethdr(how, type);
+		size = MHLEN;
+	} else {
+		m = m_get(how, type);
+		size = MLEN;
+	}
+	if (psize != NULL)
+		*psize = size;
+	return (m);
+}
+
+
+#define ET_ALIGN		0x1000
+#define ET_NSEG_MAX		32	/* XXX no limit actually */
+#define ET_NSEG_SPARE		8
+
+#define ET_TX_NDESC		512
+#define ET_RX_NDESC		512
+#define ET_RX_NRING		2
+#define ET_RX_NSTAT		(ET_RX_NRING * ET_RX_NDESC)
+
+#define ET_TX_RING_SIZE		(ET_TX_NDESC * sizeof(struct et_txdesc))
+#define ET_RX_RING_SIZE		(ET_RX_NDESC * sizeof(struct et_rxdesc))
+#define ET_RXSTAT_RING_SIZE	(ET_RX_NSTAT * sizeof(struct et_rxstat))
+
+#define ET_JUMBO_FRAMELEN	(ET_MEM_SIZE - ET_MEM_RXSIZE_MIN -	\
+				 ET_MEM_TXSIZE_EX)
+#define ET_JUMBO_MTU		(ET_JUMBO_FRAMELEN - ETHER_HDR_LEN -	\
+				 EVL_ENCAPLEN - ETHER_CRC_LEN)
+
+#define ET_FRAMELEN(mtu)	(ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) +	\
+				 ETHER_CRC_LEN)
+
+#define ET_JSLOTS		(ET_RX_NDESC + 128)
+#define ET_JLEN			(ET_JUMBO_FRAMELEN + ETHER_ALIGN)
+#define ET_JUMBO_MEM_SIZE	(ET_JSLOTS * ET_JLEN)
+
+#define CSR_WRITE_4(sc, reg, val)	\
+	bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
+#define CSR_READ_4(sc, reg)		\
+	bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
+
+#define ET_ADDR_HI(addr)	((uint64_t) (addr) >> 32)
+#define ET_ADDR_LO(addr)	((uint64_t) (addr) & 0xffffffff)
+
+struct et_txdesc {
+	uint32_t	td_addr_hi;
+	uint32_t	td_addr_lo;
+	uint32_t	td_ctrl1;	/* ET_TDCTRL1_ */
+	uint32_t	td_ctrl2;	/* ET_TDCTRL2_ */
+} __packed;
+
+#define ET_TDCTRL1_LEN		__BITS(15, 0)
+
+#define ET_TDCTRL2_LAST_FRAG	__BIT(0)
+#define ET_TDCTRL2_FIRST_FRAG	__BIT(1)
+#define ET_TDCTRL2_INTR		__BIT(2)
+
+struct et_rxdesc {
+	uint32_t	rd_addr_lo;
+	uint32_t	rd_addr_hi;
+	uint32_t	rd_ctrl;	/* ET_RDCTRL_ */
+} __packed;
+
+#define ET_RDCTRL_BUFIDX	__BITS(9, 0)
+
+struct et_rxstat {
+	uint32_t	rxst_info1;
+	uint32_t	rxst_info2;	/* ET_RXST_INFO2_ */
+} __packed;
+
+#define ET_RXST_INFO2_LEN	__BITS(15, 0)
+#define ET_RXST_INFO2_BUFIDX	__BITS(25, 16)
+#define ET_RXST_INFO2_RINGIDX	__BITS(27, 26)
+
+struct et_rxstatus {
+	uint32_t	rxs_ring;
+	uint32_t	rxs_stat_ring;	/* ET_RXS_STATRING_ */
+} __packed;
+
+#define ET_RXS_STATRING_INDEX	__BITS(27, 16)
+#define ET_RXS_STATRING_WRAP	__BIT(28)
+
+struct et_dmamap_ctx {
+	int		nsegs;
+	bus_dma_segment_t *segs;
+};
+
+struct et_txbuf {
+	struct mbuf		*tb_mbuf;
+	bus_dmamap_t		tb_dmap;
+};
+
+struct et_rxbuf {
+	struct mbuf		*rb_mbuf;
+	bus_dmamap_t		rb_dmap;
+	bus_addr_t		rb_paddr;
+};
+
+struct et_txstatus_data {
+	uint32_t		*txsd_status;
+	bus_addr_t		txsd_paddr;
+	bus_dma_tag_t		txsd_dtag;
+	bus_dmamap_t		txsd_dmap;
+};
+
+struct et_rxstatus_data {
+	struct et_rxstatus	*rxsd_status;
+	bus_addr_t		rxsd_paddr;
+	bus_dma_tag_t		rxsd_dtag;
+	bus_dmamap_t		rxsd_dmap;
+};
+
+struct et_rxstat_ring {
+	struct et_rxstat	*rsr_stat;
+	bus_addr_t		rsr_paddr;
+	bus_dma_tag_t		rsr_dtag;
+	bus_dmamap_t		rsr_dmap;
+
+	int			rsr_index;
+	int			rsr_wrap;
+};
+
+struct et_txdesc_ring {
+	struct et_txdesc	*tr_desc;
+	bus_addr_t		tr_paddr;
+	bus_dma_tag_t		tr_dtag;
+	bus_dmamap_t		tr_dmap;
+
+	int			tr_ready_index;
+	int			tr_ready_wrap;
+};
+
+struct et_rxdesc_ring {
+	struct et_rxdesc	*rr_desc;
+	bus_addr_t		rr_paddr;
+	bus_dma_tag_t		rr_dtag;
+	bus_dmamap_t		rr_dmap;
+
+	uint32_t		rr_posreg;
+	int			rr_index;
+	int			rr_wrap;
+};
+
+struct et_txbuf_data {
+	struct et_txbuf		tbd_buf[ET_TX_NDESC];
+
+	int			tbd_start_index;
+	int			tbd_start_wrap;
+	int			tbd_used;
+};
+
+struct et_softc;
+struct et_rxbuf_data;
+typedef int	(*et_newbuf_t)(struct et_rxbuf_data *, int, int);
+
+struct et_rxbuf_data {
+	struct et_rxbuf		rbd_buf[ET_RX_NDESC];
+
+	struct et_softc		*rbd_softc;
+	struct et_rxdesc_ring	*rbd_ring;
+
+	int			rbd_bufsize;
+	et_newbuf_t		rbd_newbuf;
+};
+
+struct et_softc {
+	struct ifnet		*ifp;
+	device_t		dev;
+	struct mtx		sc_mtx;
+	device_t		sc_miibus;
+	bus_space_handle_t	sc_mem_bh;
+	bus_space_tag_t		sc_mem_bt;
+	void			*sc_irq_handle;
+	struct resource		*sc_irq_res;
+	struct resource		*sc_mem_res;
+
+	struct arpcom		arpcom;
+	int			sc_if_flags;
+	uint32_t		sc_flags;	/* ET_FLAG_ */
+
+	int			sc_mem_rid;
+
+	int			sc_irq_rid;
+
+	struct callout		sc_tick;
+
+	int			watchdog_timer;
+
+	bus_dma_tag_t		sc_dtag;
+
+	struct et_rxdesc_ring	sc_rx_ring[ET_RX_NRING];
+	struct et_rxstat_ring	sc_rxstat_ring;
+	struct et_rxstatus_data	sc_rx_status;
+
+	struct et_txdesc_ring	sc_tx_ring;
+	struct et_txstatus_data	sc_tx_status;
+
+	bus_dma_tag_t		sc_mbuf_dtag;
+	bus_dmamap_t		sc_mbuf_tmp_dmap;
+	struct et_rxbuf_data	sc_rx_data[ET_RX_NRING];
+	struct et_txbuf_data	sc_tx_data;
+
+	uint32_t		sc_tx;
+	uint32_t		sc_tx_intr;
+
+	/*
+	 * Sysctl variables
+	 */
+	int			sc_rx_intr_npkts;
+	int			sc_rx_intr_delay;
+	int			sc_tx_intr_nsegs;
+	uint32_t		sc_timer;
+};
+
+#define ET_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
+#define ET_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
+#define ET_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
+
+#define ET_FLAG_TXRX_ENABLED	0x1
+#define ET_FLAG_JUMBO		0x2
+
+#endif	/* !_IF_ETVAR_H */

sys/dev/mii/miidevs

@@ -49,6 +49,7 @@ $FreeBSD$
  * mangled accordingly to compensate.
  */
 
+oui AGERE			0x00a0bc	Agere Systems
 oui ALTIMA			0x0010a9	Altima Communications
 oui AMD				0x00001a	Advanced Micro Devices
 oui ATHEROS			0x001374	Atheros Communications
@@ -106,6 +107,9 @@ oui xxREALTEK			0x000732
  * List of known models.  Grouped by oui.
  */
 
+/* Agere Systems PHYs */
+model AGERE ET1011C		0x0004 ET1011C 10/100/1000baseT PHY
+
 /* Altima Communications PHYs */
 model xxALTIMA AC101		0x0021 AC101 10/100 media interface
 model xxALTIMA AC101L		0x0012 AC101L 10/100 media interface

sys/i386/conf/GENERIC

@@ -216,6 +216,7 @@ device		bce		# Broadcom BCM5706/BCM5708 Gigabit Ethernet
 device		bfe		# Broadcom BCM440x 10/100 Ethernet
 device		bge		# Broadcom BCM570xx Gigabit Ethernet
 device		dc		# DEC/Intel 21143 and various workalikes
+device		et		# Agere ET1310 10/100/Gigabit Ethernet
 device		fxp		# Intel EtherExpress PRO/100B (82557, 82558)
 device		jme		# JMicron JMC250 Gigabit/JMC260 Fast Ethernet
 device		lge		# Level 1 LXT1001 gigabit Ethernet

sys/modules/Makefile

@@ -83,6 +83,7 @@ SUBDIR=	${_3dfx} \
 	${_em} \
 	en \
 	${_ep} \
+	${_et} \
 	${_ex} \
 	${_exca} \
 	${_ext2fs} \
@@ -396,6 +397,7 @@ _ed=		ed
 _elink=		elink
 _em=		em
 _ep=		ep
+_et=		et
 _exca=		exca
 _ext2fs=	ext2fs
 _fe=		fe
@@ -528,6 +530,7 @@ _drm=		drm
 _dtrace=	dtrace
 .endif
 _ed=		ed
+_et=		et
 _em=		em
 _exca=		exca
 _ext2fs=	ext2fs

sys/modules/et/Makefile

@@ -0,0 +1,10 @@
+# $DragonFly: src/sys/dev/netif/et/Makefile,v 1.1 2007/10/12 14:12:42 sephe Exp $
+# $FreeBSD$
+
+.PATH: ${.CURDIR}/../../dev/et
+
+KMOD=	if_et
+SRCS=	if_et.c
+SRCS+=	opt_et.h bus_if.h pci_if.h device_if.h miibus_if.h
+
+.include <bsd.kmod.mk>

sys/modules/mii/Makefile

@@ -7,7 +7,8 @@ SRCS=	acphy.c amphy.c atphy.c bmtphy.c brgphy.c bus_if.h ciphy.c device_if.h
 SRCS+=	e1000phy.c exphy.c gentbi.c icsphy.c inphy.c ip1000phy.c jmphy.c
 SRCS+=	lxtphy.c miibus_if.c miibus_if.h mii.c miidevs.h mii_physubr.c
 SRCS+=	mlphy.c nsgphy.c nsphy.c nsphyter.c pci_if.h pnaphy.c qsphy.c
-SRCS+=	rgephy.c rlphy.c ruephy.c tdkphy.c tlphy.c ukphy.c ukphy_subr.c
+SRCS+=	rgephy.c rlphy.c ruephy.c tdkphy.c tlphy.c truephy.c ukphy.c
+SRCS+=	ukphy_subr.c
 SRCS+=	xmphy.c
 
 EXPORT_SYMS=	mii_mediachg	\