Add constants for the fields in a BAR. Also, add two new macros
PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
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0ede1bfd33
commit
4dc5078f81
sys/dev
@ -220,12 +220,9 @@ ipmi2_pci_attach(device_t dev)
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return (ENXIO);
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}
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/*
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* Bottom bit of bar indicates resouce type. There should be
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* constants in pcireg.h for fields in a BAR.
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*/
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/* Check the BAR to determine our resource type. */
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sc->ipmi_io_rid = PCIR_BAR(0);
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if (pci_read_config(dev, PCIR_BAR(0), 4) & 0x1)
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if (PCI_BAR_IO(pci_read_config(dev, PCIR_BAR(0), 4)))
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type = SYS_RES_IOPORT;
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else
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type = SYS_RES_MEMORY;
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@ -72,7 +72,7 @@ __FBSDID("$FreeBSD$");
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#endif
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static uint32_t pci_mapbase(unsigned mapreg);
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static int pci_maptype(unsigned mapreg);
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static const char *pci_maptype(unsigned mapreg);
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static int pci_mapsize(unsigned testval);
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static int pci_maprange(unsigned mapreg);
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static void pci_fixancient(pcicfgregs *cfg);
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@ -305,29 +305,24 @@ pci_find_device(uint16_t vendor, uint16_t device)
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static uint32_t
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pci_mapbase(uint32_t mapreg)
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{
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int mask = 0x03;
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if ((mapreg & 0x01) == 0)
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mask = 0x0f;
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return (mapreg & ~mask);
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if (PCI_BAR_MEM(mapreg))
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return (mapreg & PCIM_BAR_MEM_BASE);
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else
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return (mapreg & PCIM_BAR_IO_BASE);
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}
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/* return map type of memory or port map */
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static int
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static const char *
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pci_maptype(unsigned mapreg)
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{
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static uint8_t maptype[0x10] = {
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PCI_MAPMEM, PCI_MAPPORT,
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PCI_MAPMEM, 0,
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PCI_MAPMEM, PCI_MAPPORT,
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0, 0,
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PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
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PCI_MAPMEM|PCI_MAPMEMP, 0,
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PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
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0, 0,
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};
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return (maptype[mapreg & 0x0f]);
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if (PCI_BAR_IO(mapreg))
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return ("I/O Port");
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if (mapreg & PCIM_BAR_MEM_PREFETCH)
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return ("Prefetchable Memory");
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return ("Memory");
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}
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/* return log2 of map size decoded for memory or port map */
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@ -355,19 +350,21 @@ static int
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pci_maprange(unsigned mapreg)
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{
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int ln2range = 0;
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switch (mapreg & 0x07) {
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case 0x00:
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case 0x01:
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case 0x05:
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if (PCI_BAR_IO(mapreg))
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ln2range = 32;
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break;
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case 0x02:
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ln2range = 20;
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break;
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case 0x04:
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ln2range = 64;
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break;
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}
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else
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switch (mapreg & PCIM_BAR_MEM_TYPE) {
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case PCIM_BAR_MEM_32:
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ln2range = 32;
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break;
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case PCIM_BAR_MEM_1MB:
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ln2range = 20;
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break;
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case PCIM_BAR_MEM_64:
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ln2range = 64;
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break;
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}
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return (ln2range);
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}
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@ -1972,7 +1969,7 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
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if (pci_maptype(map) & PCI_MAPMEM)
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if (PCI_BAR_MEM(map))
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type = SYS_RES_MEMORY;
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else
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type = SYS_RES_IOPORT;
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@ -1988,8 +1985,7 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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* areas to the type of memory involved. Memory must be at least
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* 16 bytes in size, while I/O ranges must be at least 4.
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*/
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if ((testval & 0x1) == 0x1 &&
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(testval & 0x2) != 0)
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if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
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return (barlen);
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if ((type == SYS_RES_MEMORY && ln2size < 4) ||
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(type == SYS_RES_IOPORT && ln2size < 2))
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@ -1999,7 +1995,7 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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/* Read the other half of a 64bit map register */
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base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
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if (bootverbose) {
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printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d",
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printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
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reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
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printf(", port disabled\n");
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@ -2920,7 +2916,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
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if (pci_mapbase(testval) == 0)
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goto out;
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if (pci_maptype(testval) & PCI_MAPMEM) {
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if (PCI_BAR_MEM(testval)) {
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if (type != SYS_RES_MEMORY) {
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if (bootverbose)
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device_printf(dev,
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@ -118,6 +118,19 @@
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#define PCIR_BARS 0x10
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#define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
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#define PCI_RID2BAR(rid) (((rid)-PCIR_BARS)/4)
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#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
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#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
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#define PCIM_BAR_SPACE 0x00000001
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#define PCIM_BAR_MEM_SPACE 0
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#define PCIM_BAR_IO_SPACE 1
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#define PCIM_BAR_MEM_TYPE 0x00000006
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#define PCIM_BAR_MEM_32 0
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#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
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#define PCIM_BAR_MEM_64 4
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#define PCIM_BAR_MEM_PREFETCH 0x00000008
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#define PCIM_BAR_MEM_BASE 0xfffffff0
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#define PCIM_BAR_IO_RESERVED 0x00000002
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#define PCIM_BAR_IO_BASE 0xfffffffc
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#define PCIR_CIS 0x28
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#define PCIM_CIS_ASI_MASK 0x7
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#define PCIM_CIS_ASI_TUPLE 0
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