Revamp the way that exceptional message handling is performed so that it
is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
This commit is contained in:
Justin T. Gibbs
parent
4227e01d4d
commit
4dd5dcaecd
File diff suppressed because it is too large
Load Diff
@ -34,7 +34,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: aic7xxx.h,v 1.1 1998/09/15 07:24:16 gibbs Exp $
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* $Id: aic7xxx.h,v 1.2 1998/11/23 01:33:47 gibbs Exp $
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*/
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#ifndef _AIC7XXX_H_
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@ -143,7 +143,10 @@ typedef enum {
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AHC_EXTENDED_TRANS_B = 0x200,
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AHC_TERM_ENB_A = 0x400,
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AHC_TERM_ENB_B = 0x800,
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AHC_HANDLING_REQINITS = 0x1000,
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AHC_INITIATORMODE = 0x1000,/*
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* Allow initiator operations on
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* this controller.
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*/
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AHC_TARGETMODE = 0x2000,/*
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* Allow target operations on this
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* controller.
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@ -165,11 +168,6 @@ typedef enum {
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SCB_DEVICE_RESET = 0x0004,
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SCB_SENSE = 0x0008,
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SCB_RECOVERY_SCB = 0x0040,
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SCB_MSGOUT_SENT = 0x0200,
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SCB_MSGOUT_SDTR = 0x0400,
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SCB_MSGOUT_WDTR = 0x0800,
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SCB_MSGOUT_BITS = (SCB_MSGOUT_SDTR|SCB_MSGOUT_WDTR
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|SCB_MSGOUT_SENT),
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SCB_ABORT = 0x1000,
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SCB_QUEUED_MSG = 0x2000,
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SCB_ACTIVE = 0x4000,
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@ -384,7 +382,9 @@ struct ahc_syncrate {
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typedef enum {
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MSG_TYPE_NONE = 0x00,
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MSG_TYPE_INITIATOR_MSGOUT = 0x01,
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MSG_TYPE_INITIATOR_MSGIN = 0x02
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MSG_TYPE_INITIATOR_MSGIN = 0x02,
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MSG_TYPE_TARGET_MSGOUT = 0x03,
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MSG_TYPE_TARGET_MSGIN = 0x04
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} ahc_msg_type;
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struct ahc_softc {
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@ -442,10 +442,9 @@ struct ahc_softc {
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* Per target state bitmasks.
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*/
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u_int16_t ultraenb; /* Using ultra sync rate */
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u_int16_t sdtrpending; /* Pending SDTR request */
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u_int16_t wdtrpending; /* Pending WDTR request */
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u_int16_t discenable; /* Disconnection allowed */
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u_int16_t tagenable; /* Tagged Queuing allowed */
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u_int16_t targ_msg_req; /* Need negotiation messages */
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/*
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* Hooks into the XPT.
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@ -481,10 +480,13 @@ struct ahc_softc {
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/*
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* Incoming and outgoing message handling.
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*/
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u_int8_t send_msg_perror;
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ahc_msg_type msg_type;
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u_int8_t msg_buf[8]; /* Message we are sending */
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u_int msg_len; /* Length of message to send */
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u_int msg_index; /* Current index in message */
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u_int8_t msgout_buf[8]; /* Message we are sending */
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u_int8_t msgin_buf[8]; /* Message we are receiving */
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u_int msgout_len; /* Length of message to send */
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u_int msgout_index; /* Current index in msgout */
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u_int msgin_index; /* Current index in msgin */
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/*
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* "Bus" addresses of our data structures.
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@ -32,7 +32,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: aic7xxx.reg,v 1.7 1998/09/15 07:24:16 gibbs Exp $
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* $Id: aic7xxx.reg,v 1.8 1998/11/23 01:33:47 gibbs Exp $
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*/
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/*
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@ -675,20 +675,20 @@ register INTSTAT {
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mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
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mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/
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mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
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mask EXTENDED_MSG 0x40|SEQINT /* Extended message received */
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mask ABORT_REQUESTED 0x50|SEQINT /* Reconect of aborted SCB */
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mask REJECT_MSG 0x60|SEQINT /* Reject message received */
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mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
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mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */
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mask AWAITING_MSG 0xa0|SEQINT /*
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* Kernel requested to specify
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* a message to this target
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* (command was null), so tell
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* it that it can fill the
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* message buffer.
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mask HOST_MSG_LOOP 0xa0|SEQINT /*
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* The bus is ready for the
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* host to perform another
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* message transaction. This
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* mechanism is used for things
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* like sync/wide negotiation
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* that require a kernel based
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* message state engine.
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*/
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mask TARGET_MSG_HELP 0xb0|SEQINT
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mask TARGET_SYNC_CMD 0xc0|SEQINT
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mask TRACEPOINT 0xd0|SEQINT
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mask MSGIN_PHASEMIS 0xe0|SEQINT /*
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* Target changed phase on us
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@ -1277,10 +1277,13 @@ scratch_ram {
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}
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ARG_1 {
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size 1
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mask SEND_MSG 0x80
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mask SEND_SENSE 0x40
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mask SEND_REJ 0x20
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mask MSGOUT_PHASEMIS 0x10
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mask SEND_MSG 0x80
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mask SEND_SENSE 0x40
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mask SEND_REJ 0x20
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mask MSGOUT_PHASEMIS 0x10
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mask EXIT_MSG_LOOP 0x08
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mask CONT_MSG_LOOP 0x04
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mask CONT_TARG_SESSION 0x02
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alias RETURN_1
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}
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ARG_2 {
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@ -1303,6 +1306,14 @@ scratch_ram {
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size 1
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}
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/*
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* Interrupt kernel for a message to this target on
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* the next transaction. This is usually used for
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* negotiation requests.
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*/
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TARGET_MSG_REQUEST {
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size 2
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}
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/*
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* These are reserved registers in the card's scratch ram. Some of
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@ -32,7 +32,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: aic7xxx.seq,v 1.79 1998/09/21 16:46:13 gibbs Exp $
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* $Id: aic7xxx.seq,v 1.80 1998/11/23 01:33:47 gibbs Exp $
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*/
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#include <dev/aic7xxx/aic7xxx.reg>
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@ -58,6 +58,7 @@
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reset:
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clr SCSISIGO; /* De-assert BSY */
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and SXFRCTL1, ~BITBUCKET;
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/* Always allow reselection */
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if ((ahc->flags & AHC_TARGETMODE) != 0) {
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mvi SCSISEQ, ENSELI|ENRSELI|ENAUTOATNP;
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@ -185,7 +186,7 @@ initialize_scsiid:
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and SINDEX, TARGET_SCB, SCB_CONTROL;
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or SCSISEQ, ENSELO|ENAUTOATNO|ENSELI
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|ENRSELI|ENAUTOATNP, SINDEX ret ;
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} else {
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} else if ((ahc->flags & AHC_INITIATORMODE) != 0) {
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mvi SCSISEQ, ENSELO|ENAUTOATNO|ENRSELI|ENAUTOATNP ret;
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}
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@ -216,13 +217,17 @@ selection:
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mvi CLRSINT0, CLRSELDI;
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select_in:
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if ((ahc->flags & AHC_TARGETMODE) != 0) {
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test SSTAT0, TARGET jz initiator_reselect;
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if ((ahc->flags & AHC_INITIATORMODE) != 0) {
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test SSTAT0, TARGET jz initiator_reselect;
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}
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/*
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* We've just been selected. Assert BSY and
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* setup the phase for receiving messages
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* from the target.
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*/
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mvi SCSISIGO, P_MESGOUT|BSYO;
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mvi CLRSINT1, CLRBUSFREE;
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/*
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* LAST_MSG gives an indication to the host of what
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@ -284,7 +289,7 @@ select_in:
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* initiator. We follow the guidlines from section 6.5
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* of the SCSI-2 spec for what messages are allowed when.
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*/
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call targ_inb;
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call target_inb;
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/*
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* Our first message must be one of IDENTIFY, ABORT, or
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@ -305,7 +310,7 @@ select_in:
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or SEQ_FLAGS, NO_DISCONNECT;
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test SCSISIGI, ATNI jz ident_messages_done;
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call targ_inb;
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call target_inb;
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/*
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* If this is a tagged request, the tagged message must
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* immediately follow the identify. We test for a valid
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@ -332,7 +337,7 @@ select_in:
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/*
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* Store the tag for the host.
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*/
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call targ_inb;
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call target_inb;
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if ((ahc->features & AHC_CMD_CHAN) != 0) {
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mov CCSCBRAM, DINDEX;
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} else {
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@ -340,6 +345,22 @@ select_in:
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}
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jmp ident_messages_done;
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/*
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* Pushed message loop to allow the kernel to
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* run it's own message state engine. To avoid an
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* extra nop instruction after signaling the kernel,
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* we perform the phase_lock before checking to see
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* if we should exit the loop and skip the phase_lock
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* in the ITloop. Performing back to back phase_locks
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* shouldn't hurt, but why do it twice...
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*/
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host_target_message_loop:
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mvi INTSTAT, HOST_MSG_LOOP;
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nop;
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cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
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test SSTAT0, SPIORDY jz .;
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jmp host_target_message_loop;
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more_first_messages:
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/*
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* Hmm. Now we're down to only accepting
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@ -361,6 +382,7 @@ ident_messages_done:
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mvi DFDAT, SCB_LIST_NULL;
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}
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or SEQ_FLAGS, TARG_CMD_PENDING;
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test SCSISIGI, ATNI jnz target_mesgout_pending_msg;
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jmp target_ITloop;
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/*
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@ -368,16 +390,20 @@ ident_messages_done:
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* message byte we receive so it can be checked prior to
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* driving REQ on the bus for the next byte.
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*/
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targ_inb:
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/* Drive REQ on the bus by enabling SCSI PIO */
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target_inb:
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/*
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* Drive REQ on the bus by enabling SCSI PIO.
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*/
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or SXFRCTL0, SPIOEN;
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/* Wait for the byte */
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test SSTAT0, SPIORDY jz .;
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/* Prevent our read from triggering another REQ */
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and SXFRCTL0, ~SPIOEN;
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/* Save latched contents */
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mov DINDEX, SCSIDATL ret;
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}
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if ((ahc->flags & AHC_INITIATORMODE) != 0) {
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/*
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* Reselection has been initiated by a target. Make a note that we've been
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* reselected, but haven't seen an IDENTIFY message from the target yet.
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@ -389,7 +415,7 @@ initiator_reselect:
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test SBLKCTL, SELBUSB jz . + 2;
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or SAVED_TCL, SELBUSB;
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}
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or SXFRCTL0, SPIOEN|CLRCHN;
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or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
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mvi CLRSINT1,CLRBUSFREE;
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or SIMODE1, ENBUSFREE; /*
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* We aren't expecting a
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@ -399,6 +425,7 @@ initiator_reselect:
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*/
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mvi MSG_OUT, MSG_NOOP; /* No message to send */
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jmp ITloop;
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}
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/*
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* After the selection, remove this SCB from the "waiting SCB"
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@ -410,7 +437,7 @@ select_out:
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/* Turn off the selection hardware */
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if ((ahc->flags & AHC_TARGETMODE) != 0) {
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mvi SCSISEQ, ENSELI|ENRSELI|ENAUTOATNP;
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} else {
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} else if ((ahc->flags & AHC_INITIATORMODE) != 0) {
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mvi SCSISEQ, ENRSELI|ENAUTOATNP;
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}
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mvi CLRSINT0, CLRSELDO;
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@ -425,7 +452,8 @@ select_out:
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* Assert BSY and setup the phase for
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* sending our identify messages.
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*/
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mvi SCSISIGO, P_MESGIN|BSYO;
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mvi P_MESGIN|BSYO call change_phase;
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mvi CLRSINT1,CLRBUSFREE;
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/*
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* Start out with a simple identify message.
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@ -449,9 +477,10 @@ target_synccmd:
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target_ITloop:
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/*
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* XXX Start honoring ATN signals now that
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* we properly identified ourself.
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* Start honoring ATN signals now that
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* we properly identified ourself.
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*/
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test SCSISIGI, ATNI jnz target_mesgout;
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test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase;
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test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase;
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test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase;
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@ -464,17 +493,25 @@ target_ITloop:
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if ((ahc->flags & AHC_PAGESCBS) != 0) {
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mov ALLZEROS call get_free_or_disc_scb;
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}
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mov RETURN_1, ALLZEROS;
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call complete_target_cmd;
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cmp RETURN_1, CONT_MSG_LOOP jne .;
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mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
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mov SCB_TAG call dma_scb;
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jmp target_synccmd;
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target_mesgout:
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mvi SCSISIGO, P_MESGOUT|BSYO;
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call target_inb;
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/* Local Processing goes here... */
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target_mesgout_pending_msg:
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jmp host_target_message_loop;
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target_disconnect:
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mvi SCSISIGO, P_MESGIN|BSYO;
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mvi P_MESGIN|BSYO call change_phase;
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mvi MSG_DISCONNECT call target_outb;
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target_busfree:
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and SXFRCTL0, ~SPIOEN;
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clr SCSISIGO;
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call complete_target_cmd;
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cmp LAST_MSG, MSG_NOOP je . + 2;
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@ -483,8 +520,8 @@ target_busfree:
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jmp poll_for_work;
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target_cmdphase:
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mvi SCSISIGO, P_COMMAND|BSYO;
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call targ_inb;
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mvi P_COMMAND|BSYO call change_phase;
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call target_inb;
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mov A, DINDEX;
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/* Store for host */
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if ((ahc->features & AHC_CMD_CHAN) != 0) {
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@ -528,20 +565,20 @@ target_dphase:
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* Data direction flags are from the
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* perspective of the initiator.
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*/
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and SXFRCTL0, ~SPIOEN;
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or SXFRCTL0, CLRCHN;
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mov ALLZEROS call initialize_channel;
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test SCB_TARGET_PHASES[1], TARGET_DATA_IN jz . + 4;
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mvi SCSISIGO, P_DATAIN|BSYO;
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mvi LASTPHASE, P_DATAOUT;
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mvi P_DATAIN|BSYO call change_phase;
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jmp p_data;
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mvi SCSISIGO, P_DATAOUT|BSYO;
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mvi LASTPHASE, P_DATAIN;
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mvi P_DATAOUT|BSYO call change_phase;
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jmp p_data;
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target_sphase:
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mvi SCSISIGO, P_STATUS|BSYO;
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mvi P_STATUS|BSYO call change_phase;
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mvi LASTPHASE, P_STATUS;
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mov SCB_TARGET_STATUS call target_outb;
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/* XXX Watch for ATN for parity errors??? */
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/* XXX Watch for ATN or parity errors??? */
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mvi SCSISIGO, P_MESGIN|BSYO;
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/* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
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mov ALLZEROS call target_outb;
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@ -570,29 +607,33 @@ complete_target_cmd:
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call dma_finish;
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}
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inc TQINPOS;
|
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test SEQ_FLAGS, NO_DISCONNECT jz . + 2;
|
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mvi INTSTAT,TARGET_SYNC_CMD|CMDCMPLT ret;
|
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mvi INTSTAT,CMDCMPLT ret;
|
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}
|
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|
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if ((ahc->flags & AHC_INITIATORMODE) != 0) {
|
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initiator_select:
|
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mvi SPIOEN call initialize_channel;
|
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/*
|
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* We aren't expecting a bus free, so interrupt
|
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* the kernel driver if it happens.
|
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*/
|
||||
|
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/*
|
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* We aren't expecting a bus free, so interrupt
|
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* the kernel driver if it happens.
|
||||
*/
|
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mvi CLRSINT1,CLRBUSFREE;
|
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or SIMODE1, ENBUSFREE;
|
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/*
|
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* As soon as we get a successful selection, the target should go
|
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* into the message out phase since we have ATN asserted.
|
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*/
|
||||
|
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/*
|
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* As soon as we get a successful selection, the target
|
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* should go into the message out phase since we have ATN
|
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* asserted.
|
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*/
|
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mvi MSG_OUT, MSG_IDENTIFYFLAG;
|
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or SEQ_FLAGS, IDENTIFY_SEEN;
|
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|
||||
/*
|
||||
* Main loop for information transfer phases. Wait for the target
|
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* to assert REQ before checking MSG, C/D and I/O for the bus phase.
|
||||
*/
|
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/*
|
||||
* Main loop for information transfer phases. Wait for the
|
||||
* target to assert REQ before checking MSG, C/D and I/O for
|
||||
* the bus phase.
|
||||
*/
|
||||
ITloop:
|
||||
call phase_lock;
|
||||
|
||||
@ -604,7 +645,7 @@ ITloop:
|
||||
cmp A,P_STATUS je p_status;
|
||||
cmp A,P_MESGIN je p_mesgin;
|
||||
|
||||
mvi INTSTAT,BAD_PHASE; /* unknown phase - signal driver */
|
||||
mvi INTSTAT,BAD_PHASE;
|
||||
jmp ITloop; /* Try reading the bus again. */
|
||||
|
||||
await_busfree:
|
||||
@ -615,20 +656,27 @@ await_busfree:
|
||||
test SSTAT1,REQINIT|BUSFREE jz .;
|
||||
test SSTAT1, BUSFREE jnz poll_for_work;
|
||||
mvi INTSTAT, BAD_PHASE;
|
||||
}
|
||||
|
||||
clear_target_state:
|
||||
clr DFCNTRL; /*
|
||||
* We assume that the kernel driver
|
||||
* may reset us at any time, even
|
||||
* in the middle of a DMA, so clear
|
||||
* DFCNTRL too.
|
||||
*/
|
||||
clr SCSIRATE; /*
|
||||
* We don't know the target we will
|
||||
* connect to, so default to narrow
|
||||
* transfers to avoid parity problems.
|
||||
*/
|
||||
and SXFRCTL0, ~(FAST20);
|
||||
/*
|
||||
* We assume that the kernel driver may reset us
|
||||
* at any time, even in the middle of a DMA, so
|
||||
* clear DFCNTRL too.
|
||||
*/
|
||||
clr DFCNTRL;
|
||||
|
||||
/*
|
||||
* We don't know the target we will connect to,
|
||||
* so default to narrow transfers to avoid
|
||||
* parity problems.
|
||||
*/
|
||||
if ((ahc->features & AHC_ULTRA2) != 0) {
|
||||
bmov SCSIRATE, ALLZEROS, 2;
|
||||
} else {
|
||||
clr SCSIRATE;
|
||||
and SXFRCTL0, ~(FAST20);
|
||||
}
|
||||
mvi LASTPHASE, P_BUSFREE;
|
||||
/* clear target specific flags */
|
||||
clr SEQ_FLAGS ret;
|
||||
@ -818,7 +866,12 @@ prefetched_segs_avail:
|
||||
add SG_NEXT[0],SG_SIZEOF;
|
||||
adc SG_NEXT[1],A;
|
||||
|
||||
if ((ahc->flags & AHC_TARGETMODE) != 0) {
|
||||
test SSTAT0, TARGET jnz data_phase_loop;
|
||||
}
|
||||
test SSTAT1, REQINIT jz .;
|
||||
test SSTAT1,PHASEMIS jz data_phase_loop;
|
||||
|
||||
/* Ensure the last seg is visable at the shaddow layer */
|
||||
if ((ahc->features & AHC_ULTRA2) != 0) {
|
||||
or DFCNTRL, PRELOADEN;
|
||||
@ -847,7 +900,7 @@ data_phase_finish:
|
||||
}
|
||||
|
||||
if ((ahc->flags & AHC_TARGETMODE) != 0) {
|
||||
test SEQ_FLAGS, DPHASE_PENDING jz . + 3;
|
||||
test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
|
||||
and SEQ_FLAGS, ~DPHASE_PENDING;
|
||||
jmp target_ITloop;
|
||||
}
|
||||
@ -878,6 +931,7 @@ ultra2_dmahalt:
|
||||
ret;
|
||||
}
|
||||
|
||||
if ((ahc->flags & AHC_INITIATORMODE) != 0) {
|
||||
/*
|
||||
* Command phase. Set up the DMA registers and let 'er rip.
|
||||
*/
|
||||
@ -934,17 +988,22 @@ p_status:
|
||||
jmp ITloop;
|
||||
|
||||
/*
|
||||
* Message out phase. If MSG_OUT is 0x80, build I full indentify message
|
||||
* sequence and send it to the target. In addition, if the MK_MESSAGE bit
|
||||
* is set in the SCB_CONTROL byte, interrupt the host and allow it to send
|
||||
* it's own message.
|
||||
* Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
|
||||
* indentify message sequence and send it to the target. The host may
|
||||
* override this behavior by setting the MK_MESSAGE bit in the SCB
|
||||
* control byte. This will cause us to interrupt the host and allow
|
||||
* it to handle the message phase completely on its own. If the bit
|
||||
* associated with this target is set, we will also interrupt the host,
|
||||
* thereby allowing it to send a message on the next selection regardless
|
||||
* of the transaction being sent.
|
||||
*
|
||||
* If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
|
||||
* This is done to allow the hsot to send messages outside of an identify
|
||||
* This is done to allow the host to send messages outside of an identify
|
||||
* sequence while protecting the seqencer from testing the MK_MESSAGE bit
|
||||
* on an SCB that might not be for the current nexus. (For example, a
|
||||
* BDR message in responce to a bad reselection would leave us pointed to
|
||||
* an SCB that doesn't have anything to do with the current target).
|
||||
*
|
||||
* Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
|
||||
* bus device reset).
|
||||
*
|
||||
@ -952,18 +1011,29 @@ p_status:
|
||||
* in case the target decides to put us in this phase for some strange
|
||||
* reason.
|
||||
*/
|
||||
p_mesgout_retry:
|
||||
or SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */
|
||||
p_mesgout:
|
||||
mov SINDEX, MSG_OUT;
|
||||
cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
|
||||
test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
|
||||
mov FUNCTION1, SCB_TCL;
|
||||
mov A, FUNCTION1;
|
||||
mov SINDEX, TARGET_MSG_REQUEST[0];
|
||||
if ((ahc->features & AHC_TWIN) != 0) {
|
||||
/* Second Channel uses high byte bits */
|
||||
test SCB_TCL, SELBUSB jz . + 2;
|
||||
mov SINDEX, TARGET_MSG_REQUEST[1];
|
||||
} else if ((ahc->features & AHC_WIDE) != 0) {
|
||||
test SCB_TCL, 0x80 jz . + 2; /* target > 7 */
|
||||
mov SINDEX, TARGET_MSG_REQUEST[1];
|
||||
}
|
||||
test SINDEX, A jnz host_message_loop;
|
||||
p_mesgout_identify:
|
||||
and SINDEX,LID,SCB_TCL; /* lun */
|
||||
and A,DISCENB,SCB_CONTROL; /* mask off disconnect privledge */
|
||||
or SINDEX,A; /* or in disconnect privledge */
|
||||
or SINDEX,MSG_IDENTIFYFLAG;
|
||||
p_mesgout_mk_message:
|
||||
test SCB_CONTROL,MK_MESSAGE jz p_mesgout_tag;
|
||||
mov SCSIDATL, SINDEX; /* Send the last byte */
|
||||
jmp p_mesgout_from_host + 1;/* Skip HOST_MSG test */
|
||||
/*
|
||||
* Send a tag message if TAG_ENB is set in the SCB control block.
|
||||
* Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
|
||||
@ -978,39 +1048,45 @@ p_mesgout_tag:
|
||||
cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
|
||||
mov SCB_TAG jmp p_mesgout_onebyte;
|
||||
/*
|
||||
* Interrupt the driver, and allow it to send a message
|
||||
* if it asks.
|
||||
* Interrupt the driver, and allow it to handle this message
|
||||
* phase and any required retries.
|
||||
*/
|
||||
p_mesgout_from_host:
|
||||
cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
|
||||
mvi INTSTAT,AWAITING_MSG;
|
||||
nop;
|
||||
/*
|
||||
* Did the host detect a phase change?
|
||||
*/
|
||||
cmp RETURN_1, MSGOUT_PHASEMIS je p_mesgout_done;
|
||||
jmp host_message_loop;
|
||||
|
||||
p_mesgout_onebyte:
|
||||
mvi CLRSINT1, CLRATNO;
|
||||
mov SCSIDATL, SINDEX;
|
||||
|
||||
/*
|
||||
* If the next bus phase after ATN drops is a message out, it means
|
||||
* If the next bus phase after ATN drops is message out, it means
|
||||
* that the target is requesting that the last message(s) be resent.
|
||||
*/
|
||||
call phase_lock;
|
||||
cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
|
||||
or SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */
|
||||
jmp p_mesgout;
|
||||
cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
|
||||
|
||||
p_mesgout_done:
|
||||
mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
|
||||
mov LAST_MSG, MSG_OUT;
|
||||
cmp MSG_OUT, MSG_IDENTIFYFLAG jne . + 2;
|
||||
and SCB_CONTROL, ~MK_MESSAGE;
|
||||
mvi MSG_OUT, MSG_NOOP; /* No message left */
|
||||
jmp ITloop;
|
||||
|
||||
/*
|
||||
* Pushed message loop to allow the kernel to
|
||||
* RUN IT's own message state engine. To avoid an
|
||||
* extra nop instruction after signaling the kernel,
|
||||
* we perform the phase_lock before checking to see
|
||||
* if we should exit the loop and skip the phase_lock
|
||||
* in the ITloop. Performing back to back phase_locks
|
||||
* shouldn't hurt, but why do it twice...
|
||||
*/
|
||||
host_message_loop:
|
||||
mvi INTSTAT, HOST_MSG_LOOP;
|
||||
call phase_lock;
|
||||
cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1;
|
||||
jmp host_message_loop;
|
||||
|
||||
/*
|
||||
* Message in phase. Bytes are read using Automatic PIO mode.
|
||||
*/
|
||||
@ -1022,7 +1098,7 @@ p_mesgin:
|
||||
cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
|
||||
cmp ALLZEROS,A je mesgin_complete;
|
||||
cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
|
||||
cmp A,MSG_EXTENDED je mesgin_extended;
|
||||
cmp A,MSG_EXTENDED je host_message_loop;
|
||||
cmp A,MSG_MESSAGE_REJECT je mesgin_reject;
|
||||
cmp A,MSG_NOOP je mesgin_done;
|
||||
|
||||
@ -1099,6 +1175,7 @@ complete_queue:
|
||||
add_to_free_list:
|
||||
call add_scb_to_free_list;
|
||||
jmp await_busfree;
|
||||
}
|
||||
|
||||
complete_post:
|
||||
/* Post the SCBID in SINDEX and issue an interrupt */
|
||||
@ -1113,22 +1190,9 @@ complete_post:
|
||||
if ((ahc->features & AHC_QUEUE_REGS) == 0) {
|
||||
inc QOUTPOS;
|
||||
}
|
||||
if ((ahc->flags & AHC_TARGETMODE) != 0) {
|
||||
test SEQ_FLAGS, NO_DISCONNECT jz . + 2;
|
||||
mvi INTSTAT,TARGET_SYNC_CMD|CMDCMPLT ret;
|
||||
}
|
||||
mvi INTSTAT,CMDCMPLT ret;
|
||||
|
||||
/*
|
||||
* Is it an extended message? Copy the message to our message buffer and
|
||||
* notify the host. The host will tell us whether to reject this message,
|
||||
* respond to it with the message that the host placed in our message buffer,
|
||||
* or simply to do nothing.
|
||||
*/
|
||||
mesgin_extended:
|
||||
mvi INTSTAT,EXTENDED_MSG; /* let driver know */
|
||||
jmp ITloop;
|
||||
|
||||
if ((ahc->flags & AHC_INITIATORMODE) != 0) {
|
||||
/*
|
||||
* Is it a disconnect message? Set a flag in the SCB to remind us
|
||||
* and await the bus going free.
|
||||
@ -1311,18 +1375,35 @@ inb_first:
|
||||
mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/
|
||||
inb_last:
|
||||
mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/
|
||||
}
|
||||
|
||||
if ((ahc->flags & AHC_TARGETMODE) != 0) {
|
||||
/*
|
||||
* Send a byte to an initiator in Automatic PIO mode.
|
||||
* SPIOEN must be on prior to calling this routine.
|
||||
*/
|
||||
/*
|
||||
* Change to a new phase. If we are changing the state of the I/O signal,
|
||||
* from out to in, wait an additional data release delay before continuing.
|
||||
*/
|
||||
change_phase:
|
||||
and DINDEX, IOI, SCSISIGI;
|
||||
mov SCSISIGO, SINDEX;
|
||||
and A, IOI, SINDEX;
|
||||
cmp DINDEX, A je change_phase_wait;
|
||||
test SINDEX, IOI jz change_phase_wait;
|
||||
call change_phase_wait;
|
||||
change_phase_wait:
|
||||
nop;
|
||||
nop;
|
||||
nop;
|
||||
nop ret;
|
||||
|
||||
/*
|
||||
* Send a byte to an initiator in Automatic PIO mode.
|
||||
*/
|
||||
target_outb:
|
||||
or SXFRCTL0, SPIOEN;
|
||||
test SSTAT0, SPIORDY jz .;
|
||||
mov SCSIDATL, SINDEX;
|
||||
test SSTAT0, SPIORDY jz .;
|
||||
ret;
|
||||
and SXFRCTL0, ~SPIOEN ret;
|
||||
}
|
||||
|
||||
mesgin_phasemis:
|
||||
@ -1541,8 +1622,8 @@ get_SCBID_from_host:
|
||||
phase_lock:
|
||||
test SSTAT1, REQINIT jz phase_lock;
|
||||
test SSTAT1, SCSIPERR jnz phase_lock;
|
||||
and LASTPHASE, PHASE_MASK, SCSISIGI;
|
||||
mov SCSISIGO, LASTPHASE ret;
|
||||
and SCSISIGO, PHASE_MASK, SCSISIGI;
|
||||
and LASTPHASE, PHASE_MASK, SCSISIGI ret;
|
||||
|
||||
if ((ahc->features & AHC_CMD_CHAN) == 0) {
|
||||
set_stcnt_from_hcnt:
|
||||
|
||||
@ -26,7 +26,7 @@
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id: aicasm_gram.y,v 1.4 1997/09/27 19:37:28 gibbs Exp $
|
||||
* $Id: aicasm_gram.y,v 1.5 1998/09/15 07:24:17 gibbs Exp $
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
@ -861,12 +861,12 @@ code:
|
||||
;
|
||||
|
||||
code:
|
||||
T_NOP ';'
|
||||
T_NOP ret ';'
|
||||
{
|
||||
expression_t immed;
|
||||
|
||||
make_expression(&immed, 0xff);
|
||||
format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, FALSE);
|
||||
format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, $2);
|
||||
}
|
||||
;
|
||||
|
||||
|
||||
@ -26,7 +26,7 @@
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id: aicasm_gram.y,v 1.4 1997/09/27 19:37:28 gibbs Exp $
|
||||
* $Id: aicasm_gram.y,v 1.5 1998/09/15 07:24:17 gibbs Exp $
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
@ -861,12 +861,12 @@ code:
|
||||
;
|
||||
|
||||
code:
|
||||
T_NOP ';'
|
||||
T_NOP ret ';'
|
||||
{
|
||||
expression_t immed;
|
||||
|
||||
make_expression(&immed, 0xff);
|
||||
format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, FALSE);
|
||||
format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, $2);
|
||||
}
|
||||
;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user