64-bit fixes:
(1) fix printf formats. (2) Prefer FreeBSD's MIPS_PHYS_TO_KSEG0 to hand-rolled one from Cavium. (3) Mark a few 64-bit cleanliness issues (possible). (4) Minor formatting fixes.
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@ -168,7 +168,7 @@ static inline void octeon_fpa_free (void *ptr, u_int pool,
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{
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octeon_addr_t free_ptr;
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free_ptr.word64 = (uint64_t) OCTEON_PTR2PHYS(ptr);
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free_ptr.word64 = (uint64_t)OCTEON_PTR2PHYS(ptr);
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free_ptr.sfilldidspace.didspace = OCTEON_ADDR_DIDSPACE(
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OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA, pool));
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@ -200,16 +200,15 @@ static inline void *octeon_fpa_alloc (u_int pool)
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/*
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* 32 bit FPA pointers only
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*/
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/*
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* We only use 32 bit pointers at this time
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*/
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return ((void *) OCTEON_PHYS2PTR(address & 0xffffffff));
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/*XXX mips64 issue */
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return ((void *) MIPS_PHYS_TO_KSEG0(address & 0xffffffff));
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}
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return (NULL);
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}
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static inline uint64_t octeon_fpa_alloc_phys (u_int pool)
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{
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@ -217,30 +216,4 @@ static inline uint64_t octeon_fpa_alloc_phys (u_int pool)
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pool))));
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}
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#if 0
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/*
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* octeon_fpa_alloc
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*
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* Allocate a new block from the FPA
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*
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* Buffer passes away from FPA management to SW control
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*/
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static inline void *octeon_fpa_alloc (u_int pool)
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{
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uint64_t address;
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address = oct_read64(OCTEON_ADDR_DID(OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA,
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pool)));
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if (address) {
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return ((void *) (oct_ptr_size) OCTEON_PHYS2PTR(address));
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}
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return (NULL);
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}
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#endif
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#endif /* ___OCTEON_FPA__H___ */
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@ -174,7 +174,9 @@ static void octeon_pko_doorbell_data_dump (uint64_t port)
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octeon_pko_get_port_status(port, 0, &status);
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printf("\n Port #%lld Pkts %ld Bytes %lld DoorBell %lld",
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port, status.packets, status.octets, status.doorbell);
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(unsigned long long)port, status.packets,
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(unsigned long long)status.octets,
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(unsigned long long)status.doorbell);
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}
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/*
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@ -229,7 +231,7 @@ void octeon_pko_show (u_int start_port, u_int end_port)
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printf("\n Port # %d Queue %3d [%d] BufPtr: 0x%llX Mask: %X%s",
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octeon_pko_queue_cfg.bits.port, octeon_pko_queue_cfg.bits.queue,
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octeon_pko_queue_cfg.bits.index,
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(uint64_t)octeon_pko_queue_cfg.bits.buf_ptr,
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(unsigned long long)octeon_pko_queue_cfg.bits.buf_ptr,
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octeon_pko_queue_cfg.bits.qos_mask,
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(octeon_pko_queue_cfg.bits.tail)? " Last":"");
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}
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@ -238,8 +240,6 @@ void octeon_pko_show (u_int start_port, u_int end_port)
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for (port = start_port; port < (end_port + 1); port++) {
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octeon_pko_get_port_status(port, 0, &status);
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printf("\n Port #%d Packets %ld Bytes %lld DoorBell %lld",
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port, status.packets, status.octets, status.doorbell);
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octeon_pko_doorbell_data_dump(port);
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}
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@ -696,7 +696,7 @@ static struct mbuf *octeon_rgmx_build_new_rx_mbuf (struct ifnet *ifp, void *data
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}
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if (m == m0) {
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newdata = (caddr_t) ALIGN(m->m_data + ETHER_HDR_LEN) - ETHER_HDR_LEN;
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newdata = (caddr_t)ALIGN(m->m_data + ETHER_HDR_LEN) - ETHER_HDR_LEN;
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len -= newdata - m->m_data;
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m->m_data = newdata;
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}
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@ -969,7 +969,7 @@ static u_int octeon_rgmx_pko_xmit_packet (struct rgmx_softc_dev *sc, void *out_b
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#ifdef DEBUG_TX
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printf(" temp: 0x%X ", temp);
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#endif
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xmit_cmd_ptr = (uint64_t *) OCTEON_PHYS2PTR(temp);
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xmit_cmd_ptr = (uint64_t *) MIPS_PHYS_TO_KSEG0(temp);
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xmit_cmd_index = xmit_cmd_state & OCTEON_PKO_INDEX_MASK;
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xmit_cmd_ptr += xmit_cmd_index;
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@ -423,7 +423,7 @@ static inline octeon_wqe_t *octeon_pow_work_request_sync_nocheck (octeon_pow_wai
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if (result.s_work.no_work || !result.s_work.addr) {
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return NULL;
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}
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return (octeon_wqe_t *) OCTEON_PHYS2PTR(result.s_work.addr);
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return (octeon_wqe_t *) MIPS_PHYS_TO_KSEG0(result.s_work.addr);
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}
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static inline octeon_wqe_t *octeon_pow_work_request_sync_nocheck_debug (octeon_pow_wait_t wait)
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@ -440,13 +440,14 @@ static inline octeon_wqe_t *octeon_pow_work_request_sync_nocheck_debug (octeon_p
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result.word64 = oct_read64(ptr.word64);
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printf("WQE Result: 0x%llX No-work %X Addr %llX Ptr: %p\n",
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result.word64, result.s_work.no_work, (uint64_t)result.s_work.addr,
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OCTEON_PHYS2PTR(result.s_work.addr));
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(unsigned long long)result.word64, result.s_work.no_work,
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(unsigned long long)result.s_work.addr,
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(void *)MIPS_PHYS_TO_KSEG0(result.s_work.addr));
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if (result.s_work.no_work || !result.s_work.addr) {
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return NULL;
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}
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return (octeon_wqe_t *) OCTEON_PHYS2PTR(result.s_work.addr);
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return (octeon_wqe_t *) MIPS_PHYS_TO_KSEG0(result.s_work.addr);
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}
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static inline octeon_wqe_t *octeon_pow_work_request_sync (octeon_pow_wait_t wait)
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@ -482,7 +483,7 @@ static inline octeon_wqe_t *octeon_pow_work_response_async(int scratch_addr)
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if (result.s_work.no_work) {
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return NULL;
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}
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return (octeon_wqe_t*) OCTEON_PHYS2PTR(result.s_work.addr);
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return (octeon_wqe_t*) MIPS_PHYS_TO_KSEG0(result.s_work.addr);
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}
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@ -493,18 +494,14 @@ static inline octeon_wqe_t *octeon_pow_work_response_async(int scratch_addr)
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*/
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static inline void *octeon_pow_pktptr_to_kbuffer (octeon_buf_ptr_t pkt_ptr)
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{
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return (OCTEON_PHYS2PTR(((pkt_ptr.bits.addr >> 7) - pkt_ptr.bits.back) << 7));
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return ((void *)MIPS_PHYS_TO_KSEG0(
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((pkt_ptr.bits.addr >> 7) - pkt_ptr.bits.back) << 7));
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}
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#define INTERFACE(port) (port >> 4) /* Ports 0-15 are interface 0, 16-31 are interface 1 */
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#define INDEX(port) (port & 0xf)
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#define OCTEON_RGMX_PRTX_CFG(index,interface) (0x8001180008000010ull+((index)*2048)+((interface)*0x8000000ull))
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#define OCTEON_RGMX_SMACX(offset,block_id) (0x8001180008000230ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM0(offset,block_id) (0x8001180008000180ull+((offset)*2048)+((block_id)*0x8000000ull))
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