Add LS1028A clockgen driver
The new driver provides probe and attach functions for the NXP LS1028A clockgen and passes configuration information to QorIQ clockgen class. Submitted by: Lukasz Hajec <lha@semihalf.com> Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D30125
This commit is contained in:
Marcin Wojtas
parent
ce9de47260
commit
4dfb620ea4
303
sys/arm64/qoriq/clk/ls1028a_clkgen.c
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303
sys/arm64/qoriq/clk/ls1028a_clkgen.c
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@ -0,0 +1,303 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Alstom Group.
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <arm64/qoriq/clk/qoriq_clkgen.h>
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static uint8_t ls1028a_pltfrm_pll_divs[] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0
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};
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static struct qoriq_clk_pll_def ls1028a_pltfrm_pll = {
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.clkdef = {
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.name = "ls1028a_platform_pll",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_PLATFORM_PLL, 0),
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.flags = 0
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},
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.offset = 0x60080,
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.shift = 1,
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.mask = 0xFE,
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.dividers = ls1028a_pltfrm_pll_divs,
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.flags = QORIQ_CLK_PLL_HAS_KILL_BIT
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};
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static const uint8_t ls1028a_cga_pll_divs[] = {
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2, 3, 4, 0
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};
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static struct qoriq_clk_pll_def ls1028a_cga_pll1 = {
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.clkdef = {
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.name = "ls1028a_cga_pll1",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_INTERNAL, 0),
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.flags = 0
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},
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.offset = 0x80,
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.shift = 1,
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.mask = 0xFE,
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.dividers = ls1028a_cga_pll_divs,
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.flags = QORIQ_CLK_PLL_HAS_KILL_BIT
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};
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static struct qoriq_clk_pll_def ls1028a_cga_pll2 = {
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.clkdef = {
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.name = "ls1028a_cga_pll2",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_INTERNAL, 20),
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.flags = 0
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},
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.offset = 0xA0,
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.shift = 1,
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.mask = 0xFE,
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.dividers = ls1028a_cga_pll_divs,
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.flags = QORIQ_CLK_PLL_HAS_KILL_BIT
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};
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static struct qoriq_clk_pll_def *ls1028a_cga_plls[] = {
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&ls1028a_cga_pll1,
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&ls1028a_cga_pll2
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};
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static const char *ls1028a_cmux0_parent_names[] = {
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"ls1028a_cga_pll1",
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"ls1028a_cga_pll1_div2",
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"ls1028a_cga_pll1_div4",
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NULL,
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"ls1028a_cga_pll2",
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"ls1028a_cga_pll2_div2",
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"ls1028a_cga_pll2_div4"
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};
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static struct clk_mux_def ls1028a_cmux0 = {
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.clkdef = {
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.name = "ls1028a_cmux0",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_CMUX, 0),
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.parent_names = ls1028a_cmux0_parent_names,
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.parent_cnt = nitems(ls1028a_cmux0_parent_names),
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.flags = 0
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},
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.offset = 0x70000,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static struct clk_mux_def ls1028a_cmux1 = {
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.clkdef = {
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.name = "ls1028a_cmux1",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_CMUX, 1),
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.parent_names = ls1028a_cmux0_parent_names,
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.parent_cnt = nitems(ls1028a_cmux0_parent_names),
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.flags = 0
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},
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.offset = 0x70020,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static struct clk_mux_def ls1028a_cmux2 = {
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.clkdef = {
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.name = "ls1028a_cmux2",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_CMUX, 2),
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.parent_names = ls1028a_cmux0_parent_names,
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.parent_cnt = nitems(ls1028a_cmux0_parent_names),
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.flags = 0
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},
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.offset = 0x70040,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static struct clk_mux_def ls1028a_cmux3 = {
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.clkdef = {
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.name = "ls1028a_cmux3",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_CMUX, 3),
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.parent_names = ls1028a_cmux0_parent_names,
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.parent_cnt = nitems(ls1028a_cmux0_parent_names),
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.flags = 0
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},
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.offset = 0x70060,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static const char *ls1028a_hwaccel1_parent_names[] = {
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"ls1028a_platform_pll",
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"ls1028a_cga_pll1",
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"ls1028a_cga_pll1_div2",
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"ls1028a_cga_pll1_div3",
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"ls1028a_cga_pll1_div4",
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NULL,
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"ls1028a_cga_pll2_div2",
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"ls1028a_cga_pll2_div3"
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};
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static const char *ls1028a_hwaccel2_parent_names[] = {
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"ls1028a_platform_pll",
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"ls1028a_cga_pll2",
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"ls1028a_cga_pll2_div2",
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"ls1028a_cga_pll2_div3",
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"ls1028a_cga_pll2_div4",
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NULL,
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"ls1028a_cga_pll1_div2",
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"ls1028a_cga_pll1_div3"
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};
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static struct clk_mux_def ls1028a_hwaccel1 = {
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.clkdef = {
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.name = "ls1028a_hwaccel1",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_HWACCEL, 0),
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.parent_names = ls1028a_hwaccel1_parent_names,
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.parent_cnt = nitems(ls1028a_hwaccel1_parent_names),
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.flags = 0
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},
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.offset = 0x10,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static struct clk_mux_def ls1028a_hwaccel2 = {
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.clkdef = {
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.name = "ls1028a_hwaccel2",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_HWACCEL, 1),
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.parent_names = ls1028a_hwaccel2_parent_names,
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.parent_cnt = nitems(ls1028a_hwaccel2_parent_names),
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.flags = 0
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},
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.offset = 0x30,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static struct clk_mux_def ls1028a_hwaccel3 = {
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.clkdef = {
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.name = "ls1028a_hwaccel3",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_HWACCEL, 2),
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.parent_names = ls1028a_hwaccel1_parent_names,
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.parent_cnt = nitems(ls1028a_hwaccel1_parent_names),
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.flags = 0
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},
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.offset = 0x50,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static struct clk_mux_def ls1028a_hwaccel4 = {
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.clkdef = {
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.name = "ls1028a_hwaccel4",
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.id = QORIQ_CLK_ID(QORIQ_TYPE_HWACCEL, 3),
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.parent_names = ls1028a_hwaccel2_parent_names,
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.parent_cnt = nitems(ls1028a_hwaccel2_parent_names),
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.flags = 0
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},
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.offset = 0x70,
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.shift = 27,
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.width = 4,
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.mux_flags = 0
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};
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static struct clk_mux_def *ls1028a_mux_nodes[] = {
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&ls1028a_cmux0,
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&ls1028a_cmux1,
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&ls1028a_cmux2,
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&ls1028a_cmux3,
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&ls1028a_hwaccel1,
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&ls1028a_hwaccel2,
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&ls1028a_hwaccel3,
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&ls1028a_hwaccel4
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};
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static int ls1028a_clkgen_probe(device_t);
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static int ls1028a_clkgen_attach(device_t);
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static device_method_t ls1028a_clkgen_methods[] = {
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DEVMETHOD(device_probe, ls1028a_clkgen_probe),
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DEVMETHOD(device_attach, ls1028a_clkgen_attach),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(ls1028a_clkgen, ls1028a_clkgen_driver, ls1028a_clkgen_methods,
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sizeof(struct qoriq_clkgen_softc), qoriq_clkgen_driver);
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static devclass_t ls1028a_clkgen_devclass;
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EARLY_DRIVER_MODULE(ls1028a_clkgen, simplebus, ls1028a_clkgen_driver,
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ls1028a_clkgen_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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static int
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ls1028a_clkgen_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if(!ofw_bus_is_compatible(dev, "fsl,ls1028a-clockgen"))
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return (ENXIO);
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device_set_desc(dev, "LS1028A clockgen");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ls1028a_clkgen_attach(device_t dev)
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{
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struct qoriq_clkgen_softc *sc;
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sc = device_get_softc(dev);
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sc->pltfrm_pll_def = &ls1028a_pltfrm_pll;
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sc->cga_pll = ls1028a_cga_plls;
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sc->cga_pll_num = nitems(ls1028a_cga_plls);
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sc->mux = ls1028a_mux_nodes;
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sc->mux_num = nitems(ls1028a_mux_nodes);
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sc->flags = QORIQ_LITTLE_ENDIAN;
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return (qoriq_clkgen_attach(dev));
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}
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@ -499,6 +499,7 @@ arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS
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arm64/qoriq/qoriq_dw_pci.c optional pci fdt SOC_NXP_LS
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arm64/qoriq/qoriq_therm.c optional pci fdt SOC_NXP_LS
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arm64/qoriq/qoriq_therm_if.m optional pci fdt SOC_NXP_LS
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arm64/qoriq/clk/ls1028a_clkgen.c optional clk SOC_NXP_LS
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arm64/qoriq/clk/ls1046a_clkgen.c optional clk SOC_NXP_LS
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arm64/qoriq/clk/lx2160a_clkgen.c optional clk SOC_NXP_LS
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arm64/qoriq/clk/qoriq_clk_pll.c optional clk SOC_NXP_LS
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