arm64: mv_gpio: Add Marvell 8K support
While here put the interrupts setup in it's own function
Sponsored by: Rubicon Communications, LCC ("Netgate")
This commit is contained in:
Emmanuel Vadot
parent
e1453c9e4c
commit
4f3a5b510b
@ -60,6 +60,10 @@ __FBSDID("$FreeBSD$");
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#include "gpio_if.h"
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#ifdef __aarch64__
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#include "opt_soc.h"
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#endif
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#define GPIO_MAX_INTR_COUNT 8
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#define GPIO_PINS_PER_REG 32
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#define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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@ -74,6 +78,7 @@ __FBSDID("$FreeBSD$");
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#define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS)
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struct mv_gpio_softc {
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device_t dev;
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device_t sc_busdev;
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struct resource * mem_res;
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int mem_rid;
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@ -83,6 +88,7 @@ struct mv_gpio_softc {
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void *ih_cookie[GPIO_MAX_INTR_COUNT];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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uint32_t offset;
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struct mtx mutex;
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uint8_t pin_num; /* number of GPIO pins */
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uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
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@ -189,9 +195,12 @@ static devclass_t mv_gpio_devclass;
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DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0);
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struct ofw_compat_data gpio_controllers[] = {
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{ "mrvl,gpio", (uintptr_t)true },
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{ "marvell,orion-gpio", (uintptr_t)true },
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struct ofw_compat_data compat_data[] = {
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{ "mrvl,gpio", 1 },
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{ "marvell,orion-gpio", 1 },
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#ifdef SOC_MARVELL_8K
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{ "marvell,armada-8k-gpio", 1 },
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#endif
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{ NULL, 0 }
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};
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@ -201,7 +210,7 @@ mv_gpio_probe(device_t dev)
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, gpio_controllers)->ocd_data == 0)
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Marvell Integrated GPIO Controller");
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@ -209,61 +218,75 @@ mv_gpio_probe(device_t dev)
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}
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static int
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mv_gpio_attach(device_t dev)
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mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node)
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{
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int i, size;
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struct mv_gpio_softc *sc;
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pcell_t pincnt = 0;
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pcell_t irq_cells = 0;
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phandle_t iparent;
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sc = (struct mv_gpio_softc *)device_get_softc(dev);
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if (sc == NULL)
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return (ENXIO);
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if (OF_getencprop(ofw_bus_get_node(dev), "pin-count", &pincnt,
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sizeof(pcell_t)) >= 0 ||
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OF_getencprop(ofw_bus_get_node(dev), "ngpios", &pincnt,
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sizeof(pcell_t)) >= 0) {
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sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS);
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if (bootverbose)
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device_printf(dev, "%d pins available\n", sc->pin_num);
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} else {
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device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n");
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return (ENXIO);
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}
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/* Assign generic capabilities to every gpio pin */
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for(i = 0; i < sc->pin_num; i++)
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sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP;
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pcell_t irq_cells;
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int i, size;
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/* Find root interrupt controller */
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iparent = ofw_bus_find_iparent(ofw_bus_get_node(dev));
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iparent = ofw_bus_find_iparent(node);
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if (iparent == 0) {
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device_printf(dev, "No interrupt-parrent found. "
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device_printf(sc->dev, "No interrupt-parrent found. "
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"Error in DTB\n");
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return (ENXIO);
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} else {
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/* While at parent - store interrupt cells prop */
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if (OF_searchencprop(OF_node_from_xref(iparent),
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"#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) {
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device_printf(dev, "DTB: Missing #interrupt-cells "
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device_printf(sc->dev, "DTB: Missing #interrupt-cells "
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"property in interrupt parent node\n");
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return (ENXIO);
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}
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}
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size = OF_getproplen(ofw_bus_get_node(dev), "interrupts");
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size = OF_getproplen(node, "interrupts");
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if (size != -1) {
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size = size / sizeof(pcell_t);
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size = size / irq_cells;
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sc->irq_num = size;
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device_printf(dev, "%d IRQs available\n", sc->irq_num);
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device_printf(sc->dev, "%d IRQs available\n", sc->irq_num);
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} else {
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device_printf(dev, "ERROR: no interrupts entry found!\n");
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device_printf(sc->dev, "ERROR: no interrupts entry found!\n");
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return (ENXIO);
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}
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for (i = 0; i < sc->irq_num; i++) {
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sc->irq_rid[i] = i;
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sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
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&sc->irq_rid[i], RF_ACTIVE);
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if (!sc->irq_res[i]) {
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mtx_destroy(&sc->mutex);
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device_printf(sc->dev,
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"could not allocate gpio%d interrupt\n", i+1);
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return (ENXIO);
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}
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}
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device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset);
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/* Disable all interrupts */
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bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0);
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device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset);
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bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0);
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for (i = 0; i < sc->irq_num; i++) {
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device_printf(sc->dev, "Setup intr %d\n", i);
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if (bus_setup_intr(sc->dev, sc->irq_res[i],
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INTR_TYPE_MISC,
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(driver_filter_t *)mv_gpio_intr, NULL,
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sc, &sc->ih_cookie[i]) != 0) {
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mtx_destroy(&sc->mutex);
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bus_release_resource(sc->dev, SYS_RES_IRQ,
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sc->irq_rid[i], sc->irq_res[i]);
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device_printf(sc->dev, "could not set up intr %d\n", i);
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return (ENXIO);
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}
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}
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/* Clear interrupt status. */
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device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset);
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bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0);
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sc->debounce_callouts = (struct callout **)malloc(sc->pin_num *
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sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO);
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if (sc->debounce_callouts == NULL)
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@ -274,11 +297,46 @@ mv_gpio_attach(device_t dev)
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if (sc->debounce_counters == NULL)
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return (ENOMEM);
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return (0);
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}
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static int
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mv_gpio_attach(device_t dev)
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{
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int i, rv;
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struct mv_gpio_softc *sc;
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phandle_t node;
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pcell_t pincnt = 0;
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sc = (struct mv_gpio_softc *)device_get_softc(dev);
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if (sc == NULL)
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return (ENXIO);
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node = ofw_bus_get_node(dev);
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sc->dev = dev;
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if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 ||
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OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) {
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sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS);
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if (bootverbose)
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device_printf(dev, "%d pins available\n", sc->pin_num);
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} else {
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device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n");
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return (ENXIO);
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}
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if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1)
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sc->offset = 0;
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/* Assign generic capabilities to every gpio pin */
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for(i = 0; i < sc->pin_num; i++)
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sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP;
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mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN);
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sc->mem_rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
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RF_ACTIVE);
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RF_ACTIVE | RF_SHAREABLE );
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if (!sc->mem_res) {
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mtx_destroy(&sc->mutex);
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@ -289,37 +347,9 @@ mv_gpio_attach(device_t dev)
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sc->bst = rman_get_bustag(sc->mem_res);
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sc->bsh = rman_get_bushandle(sc->mem_res);
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for (i = 0; i < sc->irq_num; i++) {
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sc->irq_rid[i] = i;
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sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&sc->irq_rid[i], RF_ACTIVE);
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if (!sc->irq_res[i]) {
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mtx_destroy(&sc->mutex);
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device_printf(dev,
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"could not allocate gpio%d interrupt\n", i+1);
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return (ENXIO);
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}
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}
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/* Disable all interrupts */
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bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0);
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bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0);
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for (i = 0; i < sc->irq_num; i++) {
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if (bus_setup_intr(dev, sc->irq_res[i],
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INTR_TYPE_MISC,
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(driver_filter_t *)mv_gpio_intr, NULL,
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sc, &sc->ih_cookie[i]) != 0) {
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mtx_destroy(&sc->mutex);
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bus_release_resource(dev, SYS_RES_IRQ,
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sc->irq_rid[i], sc->irq_res[i]);
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device_printf(dev, "could not set up intr %d\n", i);
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return (ENXIO);
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}
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}
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/* Clear interrupt status. */
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bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0);
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rv = mv_gpio_setup_interrupts(sc, node);
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if (rv != 0)
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return (rv);
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sc->sc_busdev = gpiobus_attach_bus(dev);
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if (sc->sc_busdev == NULL) {
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@ -540,6 +570,8 @@ mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask)
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return (EINVAL);
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if (mask & MV_GPIO_IN_DEBOUNCE) {
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if (sc->irq_num == 0)
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return (EINVAL);
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error = mv_gpio_debounce_prepare(dev, pin);
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if (error != 0)
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return (error);
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@ -845,7 +877,7 @@ mv_gpio_reg_read(device_t dev, uint32_t reg)
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struct mv_gpio_softc *sc;
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sc = (struct mv_gpio_softc *)device_get_softc(dev);
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return (bus_space_read_4(sc->bst, sc->bsh, reg));
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return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg));
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}
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static void
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@ -854,7 +886,7 @@ mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val)
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struct mv_gpio_softc *sc;
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sc = (struct mv_gpio_softc *)device_get_softc(dev);
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bus_space_write_4(sc->bst, sc->bsh, reg, val);
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bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val);
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}
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static void
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@ -204,6 +204,7 @@ device aw_gpio # Allwinner GPIO controller
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device gpio
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device gpioled
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device fdt_pinctrl
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device mv_gpio # Marvell GPIO controller
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device mvebu_pinctrl # Marvell Pinmux Controller
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# I2C
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@ -89,6 +89,7 @@ arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt
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arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt
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arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt
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arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837
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arm/mv/gpio.c optional mv_gpio fdt
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arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt
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arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt
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arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
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