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Invalidate TLBs explicitly. r1.4 of sys/i386/i386/i686_mem.c removed this

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code but probably it only worked by chance because modifying CR4.PGE bit
causes invlidation of entire TLBs.  Since these are very rare events, this
micro-optimization seems useless.

Reviewed by:	jhb
This commit is contained in:
Jung-uk Kim 2010-11-16 22:44:58 +00:00
parent 7d31a76295
commit 50083a5624
2 changed files with 6 additions and 2 deletions
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4
sys/amd64/amd64/amd64_mem.c
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@ -321,6 +321,7 @@ amd64_mrstoreone(void *arg)
/* Flushes caches and TLBs. */
wbinvd();
invltlb();
/* Disable MTRRs (E = 0). */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
@ -388,8 +389,9 @@ amd64_mrstoreone(void *arg)
wrmsr(msr + 1, msrv);
}
/* Flush caches, TLBs. */
/* Flush caches and TLBs. */
wbinvd();
invltlb();
/* Enable MTRRs. */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);

4
sys/i386/i386/i686_mem.c
View File

@ -315,6 +315,7 @@ i686_mrstoreone(void *arg)
/* Flushes caches and TLBs. */
wbinvd();
invltlb();
/* Disable MTRRs (E = 0). */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
@ -382,8 +383,9 @@ i686_mrstoreone(void *arg)
wrmsr(msr + 1, msrv);
}
/* Flush caches, TLBs. */
/* Flush caches and TLBs. */
wbinvd();
invltlb();
/* Enable MTRRs. */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);