d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add a driver for the Chelsio T6 crypto accelerator engine.

Browse Source 
The ccr(4) driver supports use of the crypto accelerator engine on
Chelsio T6 NICs in "lookaside" mode via the opencrypto framework.

Currently, the driver supports AES-CBC, AES-CTR, AES-GCM, and AES-XTS
cipher algorithms as well as the SHA1-HMAC, SHA2-256-HMAC, SHA2-384-HMAC,
and SHA2-512-HMAC authentication algorithms.  The driver also supports
chaining one of AES-CBC, AES-CTR, or AES-XTS with an authentication
algorithm for encrypt-then-authenticate operations.

Note that this driver is still under active development and testing and
may not yet be ready for production use.  It does pass the tests in
tests/sys/opencrypto with the exception that the AES-GCM implementation
in the driver does not yet support requests with a zero byte payload.

To use this driver currently, the "uwire" configuration must be used
along with explicitly enabling support for lookaside crypto capabilities
in the cxgbe(4) driver.  These can be done by setting the following
tunables before loading the cxgbe(4) driver:

    hw.cxgbe.config_file=uwire
    hw.cxgbe.cryptocaps_allowed=-1

MFC after:	1 month
Relnotes:	yes
Sponsored by:	Chelsio Communications
Differential Revision:	https://reviews.freebsd.org/D10763
This commit is contained in:
John Baldwin 2017-05-17 22:13:07 +00:00
parent c1212a7a74
commit 5033c43b7a
11 changed files with 2427 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
share/man/man4/Makefile
View File

@ -100,6 +100,7 @@ MAN= aac.4 \
cc_newreno.4 \
cc_vegas.4 \
${_ccd.4} \
ccr.4 \
cd.4 \
cdce.4 \
cfi.4 \

110
share/man/man4/ccr.4 Normal file
View File

@ -0,0 +1,110 @@
.\" Copyright (c) 2017, Chelsio Inc
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd May 16, 2017
.Dt CCR 4
.Os
.Sh NAME
.Nm ccr
.Nd "Chelsio T6 crypto accelerator driver"
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indeunt
.Cd "device ccr"
.Ed
.Pp
To load the driver as a
module at boot time, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
ccr_load="YES"
.Ed
.Sh DESCRIPTION
The
.Nm
driver provides support for the crypto accelerator engine included on
PCI Express Ethernet adapters based on the Chelsio Terminator 6 ASIC (T6).
The driver accelerates AES-CBC, AES-CTR, AES-GCM, AES-XTS, SHA1-HMAC,
SHA2-256-HMAC, SHA2-384-HMAC, and SHA2-512-HMAC operations for
.Xr crypto 4
and
.Xr ipsec 4 .
The driver also supports chaining one of AES-CBC, AES-CTR, or AES-XTS with
SHA1-HMAC, SHA2-256-HMAC, SHA2-384-HMAC, or SHA2-512-HMAC for
encrypt-then-authenticate operations.
For further hardware information and questions related to hardware
requirements, see
.Pa http://www.chelsio.com/ .
.Pp
The
.Nm
driver attaches as a child of an existing Chelsio NIC device and thus
requires that the
.Xr cxgbe 4
driver be active.
.Sh HARDWARE
The
.Nm
driver supports the crypto accelerator engine included on adapters
based on the T6 ASIC:
.Pp
.Bl -bullet -compact
.It
Chelsio T6225-CR
.It
Chelsio T6225-SO-CR
.It
Chelsio T62100-LP-CR
.It
Chelsio T62100-SO-CR
.It
Chelsio T62100-CR
.El
.Sh SUPPORT
For general information and support,
go to the Chelsio support website at:
.Pa http://www.chelsio.com/ .
.Pp
If an issue is identified with this driver with a supported adapter,
email all the specific information related to the issue to
.Aq Mt support@chelsio.com .
.Sh SEE ALSO
.Xr crypto 4 ,
.Xr cxgbe 4 ,
.Xr ipsec 4
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 12.0 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was written by
.An John Baldwin Aq Mt jhb@FreeBSD.org .

3
share/man/man4/cxgbe.4
View File

@ -31,7 +31,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd December 22, 2016
.Dd May 16, 2017
.Dt CXGBE 4
.Os
.Sh NAME
@ -367,6 +367,7 @@ email all the specific information related to the issue to
.Sh SEE ALSO
.Xr altq 4 ,
.Xr arp 4 ,
.Xr ccr 4 ,
.Xr cxgb 4 ,
.Xr cxgbev 4 ,
.Xr netintro 4 ,

2
sys/conf/NOTES
View File

@ -2849,6 +2849,8 @@ device cryptodev # /dev/crypto for access to h/w
device rndtest # FIPS 140-2 entropy tester
device ccr # Chelsio T6
device hifn # Hifn 7951, 7781, etc.
options HIFN_DEBUG # enable debugging support: hw.hifn.debug
options HIFN_RNDTEST # enable rndtest support

2
sys/conf/files
View File

@ -1428,6 +1428,8 @@ t6fw.fw optional cxgbe \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "t6fw.fw"
dev/cxgbe/crypto/t4_crypto.c optional ccr \
compile-with "${NORMAL_C} -I$S/dev/cxgbe"
dev/cy/cy.c optional cy
dev/cy/cy_isa.c optional cy isa
dev/cy/cy_pci.c optional cy pci

1
sys/dev/cxgbe/adapter.h
View File

@ -796,6 +796,7 @@ struct adapter {
struct tom_tunables tt;
void *iwarp_softc; /* (struct c4iw_dev *) */
void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
void *ccr_softc; /* (struct ccr_softc *) */
struct l2t_data *l2t; /* L2 table */
struct tid_info tids;

2102
sys/dev/cxgbe/crypto/t4_crypto.c Normal file
View File

File diff suppressed because it is too large Load Diff

186
sys/dev/cxgbe/crypto/t4_crypto.h Normal file
View File

@ -0,0 +1,186 @@
/*-
* Copyright (c) 2017 Chelsio Communications, Inc.
* All rights reserved.
* Written by: John Baldwin <jhb@FreeBSD.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef __T4_CRYPTO_H__
#define __T4_CRYPTO_H__
/* From chr_core.h */
#define PAD_ERROR_BIT 1
#define CHK_PAD_ERR_BIT(x) (((x) >> PAD_ERROR_BIT) & 1)
#define MAC_ERROR_BIT 0
#define CHK_MAC_ERR_BIT(x) (((x) >> MAC_ERROR_BIT) & 1)
#define MAX_SALT 4
struct _key_ctx {
__be32 ctx_hdr;
u8 salt[MAX_SALT];
__be64 reserverd;
unsigned char key[0];
};
struct chcr_wr {
struct fw_crypto_lookaside_wr wreq;
struct ulp_txpkt ulptx;
struct ulptx_idata sc_imm;
struct cpl_tx_sec_pdu sec_cpl;
struct _key_ctx key_ctx;
};
/* From chr_algo.h */
/* Crypto key context */
#define S_KEY_CONTEXT_CTX_LEN 24
#define M_KEY_CONTEXT_CTX_LEN 0xff
#define V_KEY_CONTEXT_CTX_LEN(x) ((x) << S_KEY_CONTEXT_CTX_LEN)
#define G_KEY_CONTEXT_CTX_LEN(x) \
(((x) >> S_KEY_CONTEXT_CTX_LEN) & M_KEY_CONTEXT_CTX_LEN)
#define S_KEY_CONTEXT_DUAL_CK 12
#define M_KEY_CONTEXT_DUAL_CK 0x1
#define V_KEY_CONTEXT_DUAL_CK(x) ((x) << S_KEY_CONTEXT_DUAL_CK)
#define G_KEY_CONTEXT_DUAL_CK(x) \
(((x) >> S_KEY_CONTEXT_DUAL_CK) & M_KEY_CONTEXT_DUAL_CK)
#define F_KEY_CONTEXT_DUAL_CK V_KEY_CONTEXT_DUAL_CK(1U)
#define S_KEY_CONTEXT_OPAD_PRESENT 11
#define M_KEY_CONTEXT_OPAD_PRESENT 0x1
#define V_KEY_CONTEXT_OPAD_PRESENT(x) ((x) << S_KEY_CONTEXT_OPAD_PRESENT)
#define G_KEY_CONTEXT_OPAD_PRESENT(x) \
(((x) >> S_KEY_CONTEXT_OPAD_PRESENT) & \
M_KEY_CONTEXT_OPAD_PRESENT)
#define F_KEY_CONTEXT_OPAD_PRESENT V_KEY_CONTEXT_OPAD_PRESENT(1U)
#define S_KEY_CONTEXT_SALT_PRESENT 10
#define M_KEY_CONTEXT_SALT_PRESENT 0x1
#define V_KEY_CONTEXT_SALT_PRESENT(x) ((x) << S_KEY_CONTEXT_SALT_PRESENT)
#define G_KEY_CONTEXT_SALT_PRESENT(x) \
(((x) >> S_KEY_CONTEXT_SALT_PRESENT) & \
M_KEY_CONTEXT_SALT_PRESENT)
#define F_KEY_CONTEXT_SALT_PRESENT V_KEY_CONTEXT_SALT_PRESENT(1U)
#define S_KEY_CONTEXT_CK_SIZE 6
#define M_KEY_CONTEXT_CK_SIZE 0xf
#define V_KEY_CONTEXT_CK_SIZE(x) ((x) << S_KEY_CONTEXT_CK_SIZE)
#define G_KEY_CONTEXT_CK_SIZE(x) \
(((x) >> S_KEY_CONTEXT_CK_SIZE) & M_KEY_CONTEXT_CK_SIZE)
#define S_KEY_CONTEXT_MK_SIZE 2
#define M_KEY_CONTEXT_MK_SIZE 0xf
#define V_KEY_CONTEXT_MK_SIZE(x) ((x) << S_KEY_CONTEXT_MK_SIZE)
#define G_KEY_CONTEXT_MK_SIZE(x) \
(((x) >> S_KEY_CONTEXT_MK_SIZE) & M_KEY_CONTEXT_MK_SIZE)
#define S_KEY_CONTEXT_VALID 0
#define M_KEY_CONTEXT_VALID 0x1
#define V_KEY_CONTEXT_VALID(x) ((x) << S_KEY_CONTEXT_VALID)
#define G_KEY_CONTEXT_VALID(x) \
(((x) >> S_KEY_CONTEXT_VALID) & \
M_KEY_CONTEXT_VALID)
#define F_KEY_CONTEXT_VALID V_KEY_CONTEXT_VALID(1U)
#define CHCR_HASH_MAX_DIGEST_SIZE 64
#define DUMMY_BYTES 16
#define TRANSHDR_SIZE(kctx_len)\
(sizeof(struct chcr_wr) +\
kctx_len)
#define CIPHER_TRANSHDR_SIZE(kctx_len, sge_pairs) \
(TRANSHDR_SIZE((kctx_len)) + (sge_pairs) +\
sizeof(struct cpl_rx_phys_dsgl))
#define HASH_TRANSHDR_SIZE(kctx_len)\
(TRANSHDR_SIZE(kctx_len) + DUMMY_BYTES)
#define CRYPTO_MAX_IMM_TX_PKT_LEN 256
struct phys_sge_pairs {
__be16 len[8];
__be64 addr[8];
};
/* From chr_crypto.h */
#define CHCR_AES_MAX_KEY_LEN (AES_XTS_MAX_KEY)
#define CHCR_MAX_CRYPTO_IV_LEN 16 /* AES IV len */
#define CHCR_ENCRYPT_OP 0
#define CHCR_DECRYPT_OP 1
#define CHCR_SCMD_PROTO_VERSION_GENERIC 4
#define CHCR_SCMD_CIPHER_MODE_NOP 0
#define CHCR_SCMD_CIPHER_MODE_AES_CBC 1
#define CHCR_SCMD_CIPHER_MODE_AES_GCM 2
#define CHCR_SCMD_CIPHER_MODE_AES_CTR 3
#define CHCR_SCMD_CIPHER_MODE_GENERIC_AES 4
#define CHCR_SCMD_CIPHER_MODE_AES_XTS 6
#define CHCR_SCMD_CIPHER_MODE_AES_CCM 7
#define CHCR_SCMD_AUTH_MODE_NOP 0
#define CHCR_SCMD_AUTH_MODE_SHA1 1
#define CHCR_SCMD_AUTH_MODE_SHA224 2
#define CHCR_SCMD_AUTH_MODE_SHA256 3
#define CHCR_SCMD_AUTH_MODE_GHASH 4
#define CHCR_SCMD_AUTH_MODE_SHA512_224 5
#define CHCR_SCMD_AUTH_MODE_SHA512_256 6
#define CHCR_SCMD_AUTH_MODE_SHA512_384 7
#define CHCR_SCMD_AUTH_MODE_SHA512_512 8
#define CHCR_SCMD_AUTH_MODE_CBCMAC 9
#define CHCR_SCMD_AUTH_MODE_CMAC 10
#define CHCR_SCMD_HMAC_CTRL_NOP 0
#define CHCR_SCMD_HMAC_CTRL_NO_TRUNC 1
#define CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366 2
#define CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT 3
#define CHCR_SCMD_HMAC_CTRL_PL1 4
#define CHCR_SCMD_HMAC_CTRL_PL2 5
#define CHCR_SCMD_HMAC_CTRL_PL3 6
#define CHCR_SCMD_HMAC_CTRL_DIV2 7
/* This are not really mac key size. They are intermediate values
* of sha engine and its size
*/
#define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
#define CHCR_KEYCTX_MAC_KEY_SIZE_160 1
#define CHCR_KEYCTX_MAC_KEY_SIZE_192 2
#define CHCR_KEYCTX_MAC_KEY_SIZE_256 3
#define CHCR_KEYCTX_MAC_KEY_SIZE_512 4
#define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
#define CHCR_KEYCTX_CIPHER_KEY_SIZE_192 1
#define CHCR_KEYCTX_CIPHER_KEY_SIZE_256 2
#define CHCR_KEYCTX_NO_KEY 15
#define IV_NOP 0
#define IV_IMMEDIATE 1
#define IV_DSGL 2
#define CHCR_HASH_MAX_BLOCK_SIZE_64 64
#define CHCR_HASH_MAX_BLOCK_SIZE_128 128
#endif /* !__T4_CRYPTO_H__ */

1
sys/modules/cxgbe/Makefile
View File

@ -17,6 +17,7 @@ SUBDIR+= t6_firmware
SUBDIR+= ${_tom}
SUBDIR+= ${_iw_cxgbe}
SUBDIR+= ${_cxgbei}
SUBDIR+= ccr
.if ${MACHINE_CPUARCH} == "amd64"
_tom= tom

19
sys/modules/cxgbe/ccr/Makefile Normal file
View File

@ -0,0 +1,19 @@
# $FreeBSD$
CXGBE= ${SRCTOP}/sys/dev/cxgbe
.PATH: ${CXGBE}/crypto
KMOD= ccr
SRCS= t4_crypto.c
SRCS+= bus_if.h
SRCS+= device_if.h
SRCS+= cryptodev_if.h
SRCS+= pci_if.h
CFLAGS+= -I${CXGBE}
MFILES= kern/bus_if.m kern/device_if.m opencrypto/cryptodev_if.m \
dev/pci/pci_if.m
.include <bsd.kmod.mk>

1
sys/powerpc/conf/NOTES
View File

@ -76,6 +76,7 @@ device adm1030 # Apple G4 MDD fan controller
# Devices we don't want to deal with
nodevice bktr
nodevice ccr
nodevice cxgbe # XXX: builds on powerpc64 only.
nodevice cxgbev
nodevice fdc