- Split db.desc.cmd into desc.control and desc.reqcount.
- remove unncessary descriptor updates.
This commit is contained in:
parent
23e8074bd0
commit
53f1eb8620
@ -828,7 +828,8 @@ fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
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}
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db = &db_tr->db[0];
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db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len;
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db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2;
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db->db.desc.reqcount = hdr_len;
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db->db.desc.status = 0;
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/* Specify bound timer of asy. responce */
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if(&sc->atrs == dbch){
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@ -842,8 +843,8 @@ fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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if (xfer->mbuf == NULL) {
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db->db.desc.addr
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= vtophys(xfer->send.buf + xfer->send.off) + hdr_off;
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db->db.desc.cmd
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= OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff);
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db->db.desc.control = OHCI_OUTPUT_MORE;
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db->db.desc.reqcount = len - hdr_off;
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db->db.desc.status = 0;
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db_tr->dbcnt++;
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@ -859,7 +860,8 @@ fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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continue;
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db->db.desc.addr
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= vtophys(mtod(m, caddr_t));
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db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len;
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db->db.desc.control = OHCI_OUTPUT_MORE;
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db->db.desc.reqcount = m->m_len;
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db->db.desc.status = 0;
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db++;
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db_tr->dbcnt++;
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@ -878,7 +880,7 @@ fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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}
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/* last db */
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LAST_DB(db_tr, db);
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db->db.desc.cmd |= OHCI_OUTPUT_LAST
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db->db.desc.control |= OHCI_OUTPUT_LAST
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| OHCI_INTERRUPT_ALWAYS
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| OHCI_BRANCH_ALWAYS;
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db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db);
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@ -1298,6 +1300,7 @@ fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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int idb, z, i, dmach = 0;
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u_int32_t off = NULL;
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struct fwohcidb_tr *db_tr;
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volatile struct fwohcidb *db;
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if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
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err = EINVAL;
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@ -1328,20 +1331,19 @@ fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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if(STAILQ_NEXT(db_tr, link) == NULL){
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break;
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}
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db_tr->db[0].db.desc.depend
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= vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
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db_tr->db[db_tr->dbcnt - 1].db.desc.depend
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db = db_tr->db;
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db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend
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= vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
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if(dbch->xferq.flag & FWXFERQ_EXTBUF){
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if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
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db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
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db[db_tr->dbcnt - 1].db.desc.control
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|= OHCI_INTERRUPT_ALWAYS;
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db_tr->db[0].db.desc.depend &= ~0xf;
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db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
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~0xf;
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/* OHCI 1.1 and above */
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db_tr->db[0].db.desc.cmd
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|= OHCI_INTERRUPT_ALWAYS;
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db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
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#if 0
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db[0].db.desc.depend &= ~0xf;
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db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf;
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#endif
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}
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}
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db_tr = STAILQ_NEXT(db_tr, link);
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@ -1354,9 +1356,10 @@ static int
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fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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{
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int err = 0;
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int idb, z, i, dmach = 0;
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int idb, z, i, dmach = 0, ldesc;
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u_int32_t off = NULL;
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struct fwohcidb_tr *db_tr;
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volatile struct fwohcidb *db;
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z = dbch->ndesc;
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if(&sc->arrq == dbch){
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@ -1403,14 +1406,15 @@ fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
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if(STAILQ_NEXT(db_tr, link) == NULL){
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break;
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}
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db_tr->db[db_tr->dbcnt - 1].db.desc.depend
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db = db_tr->db;
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ldesc = db_tr->dbcnt - 1;
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db[ldesc].db.desc.depend
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= vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
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if(dbch->xferq.flag & FWXFERQ_EXTBUF){
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if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
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db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
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db[ldesc].db.desc.control
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|= OHCI_INTERRUPT_ALWAYS;
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db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
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~0xf;
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db[ldesc].db.desc.depend &= ~0xf;
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}
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}
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db_tr = STAILQ_NEXT(db_tr, link);
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@ -1481,24 +1485,31 @@ fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
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if(err)
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return err;
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ldesc = dbch->ndesc - 1;
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s = splfw();
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prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
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while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
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volatile struct fwohcidb *db;
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fwohci_txbufdb(sc, dmach, chunk);
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ldesc = dbch->ndesc - 1;
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#if 0
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db = ((struct fwohcidb_tr *)(chunk->end))->db;
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db[ldesc].db.desc.status = db[0].db.desc.status = 0;
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db[ldesc].db.desc.count = db[0].db.desc.count = 0;
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db[ldesc].db.desc.depend &= ~0xf;
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db[0].db.desc.depend &= ~0xf;
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#endif
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if (prev != NULL) {
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db = ((struct fwohcidb_tr *)(prev->end))->db;
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db[ldesc].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
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db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS;
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#if 0 /* if bulkxfer->npacket changes */
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db[ldesc].db.desc.depend = db[0].db.desc.depend =
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vtophys(((struct fwohcidb_tr *)
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(chunk->start))->db) | dbch->ndesc;
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#else
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db[0].db.desc.depend |= dbch->ndesc;
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db[ldesc].db.desc.depend |= dbch->ndesc;
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#endif
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}
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STAILQ_REMOVE_HEAD(&it->stvalid, link);
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STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
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@ -1615,9 +1626,13 @@ fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
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db[ldesc].db.desc.depend &= ~0xf;
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if (prev != NULL) {
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db = ((struct fwohcidb_tr *)(prev->end))->db;
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#if 0
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db[ldesc].db.desc.depend =
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vtophys(((struct fwohcidb_tr *)
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(chunk->start))->db) | dbch->ndesc;
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#else
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db[ldesc].db.desc.depend |= dbch->ndesc;
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#endif
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}
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STAILQ_REMOVE_HEAD(&ir->stfree, link);
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STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
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@ -2209,18 +2224,18 @@ print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max)
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"Stat",
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"Cnt");
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for( i = 0 ; i <= max ; i ++){
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key = db[i].db.desc.cmd & OHCI_KEY_MASK;
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key = db[i].db.desc.control & OHCI_KEY_MASK;
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#if __FreeBSD_version >= 500000
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printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x",
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#else
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printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
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#endif
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vtophys(&db[i]),
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dbcode[(db[i].db.desc.cmd >> 28) & 0xf],
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dbkey[(db[i].db.desc.cmd >> 24) & 0x7],
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dbcond[(db[i].db.desc.cmd >> 20) & 0x3],
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dbcond[(db[i].db.desc.cmd >> 18) & 0x3],
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db[i].db.desc.cmd & 0xffff,
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dbcode[(db[i].db.desc.control >> 12) & 0xf],
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dbkey[(db[i].db.desc.control >> 8) & 0x7],
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dbcond[(db[i].db.desc.control >> 4) & 0x3],
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dbcond[(db[i].db.desc.control >> 2) & 0x3],
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db[i].db.desc.reqcount,
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db[i].db.desc.addr,
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db[i].db.desc.depend,
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db[i].db.desc.status,
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@ -2250,15 +2265,15 @@ print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max)
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if(key == OHCI_KEY_DEVICE){
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return;
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}
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if((db[i].db.desc.cmd & OHCI_BRANCH_MASK)
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if((db[i].db.desc.control & OHCI_BRANCH_MASK)
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== OHCI_BRANCH_ALWAYS){
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return;
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}
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if((db[i].db.desc.cmd & OHCI_CMD_MASK)
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if((db[i].db.desc.control & OHCI_CMD_MASK)
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== OHCI_OUTPUT_LAST){
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return;
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}
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if((db[i].db.desc.cmd & OHCI_CMD_MASK)
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if((db[i].db.desc.control & OHCI_CMD_MASK)
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== OHCI_INPUT_LAST){
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return;
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}
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@ -2297,6 +2312,7 @@ fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
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{
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struct fwohcidb_tr *db_tr, *fdb_tr;
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struct fwohci_dbch *dbch;
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volatile struct fwohcidb *db;
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struct fw_pkt *fp;
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volatile struct fwohci_txpkthdr *ohcifp;
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unsigned short chtag;
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@ -2311,41 +2327,48 @@ fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
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device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db));
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*/
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for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){
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db_tr->db[0].db.desc.cmd
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= OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
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db = db_tr->db;
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#if 0
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db[0].db.desc.control
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= OHCI_OUTPUT_MORE | OHCI_KEY_ST2;
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db[0].db.desc.reqcount = 8;
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#endif
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fp = (struct fw_pkt *)db_tr->buf;
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ohcifp = (volatile struct fwohci_txpkthdr *)
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db_tr->db[1].db.immed;
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ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed;
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ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]);
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ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
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ohcifp->mode.stream.chtag = chtag;
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ohcifp->mode.stream.tcode = 0xa;
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ohcifp->mode.stream.spd = 0;
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db_tr->db[2].db.desc.cmd
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= OHCI_OUTPUT_LAST
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db[2].db.desc.reqcount = ntohs(fp->mode.stream.len);
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db[2].db.desc.status = 0;
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db[2].db.desc.count = 0;
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#if 0 /* if bulkxfer->npackets changes */
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db[2].db.desc.control = OHCI_OUTPUT_LAST
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| OHCI_UPDATE
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| OHCI_BRANCH_ALWAYS
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| ((ntohs(fp->mode.stream.len) ) & 0xffff);
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db_tr->db[2].db.desc.status = 0;
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db_tr->db[2].db.desc.count = 0;
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db_tr->db[0].db.desc.depend
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= vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
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db_tr->db[dbch->ndesc - 1].db.desc.depend
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| OHCI_BRANCH_ALWAYS;
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db[0].db.desc.depend =
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= db[dbch->ndesc - 1].db.desc.depend
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= vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
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#else
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db[0].db.desc.depend |= dbch->ndesc;
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db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc;
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#endif
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bulkxfer->end = (caddr_t)db_tr;
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db_tr = STAILQ_NEXT(db_tr, link);
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}
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db_tr = (struct fwohcidb_tr *)bulkxfer->end;
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db_tr->db[0].db.desc.depend &= ~0xf;
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db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
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db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS;
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db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
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db[0].db.desc.depend &= ~0xf;
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db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
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#if 0 /* if bulkxfer->npackets changes */
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db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
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/* OHCI 1.1 and above */
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db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS;
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db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
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#endif
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/*
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db_tr = (struct fwohcidb_tr *)bulkxfer->start;
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fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
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/*
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device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db));
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*/
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return;
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@ -2365,25 +2388,24 @@ fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size,
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db_tr->dbcnt = 3;
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db_tr->dummy = NULL;
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db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
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db[2].db.desc.depend = 0;
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db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2;
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db[0].db.desc.reqcount = 8;
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db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t);
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db[2].db.desc.cmd = OHCI_OUTPUT_MORE;
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db[2].db.desc.control =
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OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS;
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#if 1
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db[0].db.desc.status = 0;
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db[0].db.desc.count = 0;
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db[2].db.desc.status = 0;
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db[2].db.desc.count = 0;
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#endif
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if( mode & FWXFERQ_STREAM ){
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db[2].db.desc.cmd |= OHCI_OUTPUT_LAST;
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if(mode & FWXFERQ_PACKET ){
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db[2].db.desc.cmd
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|= OHCI_INTERRUPT_ALWAYS;
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db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
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}
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} else {
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printf("fwohci_add_tx_buf: who calls me?");
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}
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db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
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return 1;
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}
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@ -2421,21 +2443,22 @@ fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode,
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}
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for(i = 0 ; i < db_tr->dbcnt ; i++){
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db[i].db.desc.addr = vtophys(dbuf[i]) ;
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db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i];
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db[i].db.desc.control = OHCI_INPUT_MORE;
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db[i].db.desc.reqcount = dsiz[i];
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if( mode & FWXFERQ_STREAM ){
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db[i].db.desc.cmd |= OHCI_UPDATE;
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db[i].db.desc.control |= OHCI_UPDATE;
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}
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db[i].db.desc.status = 0;
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db[i].db.desc.count = dsiz[i];
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}
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if( mode & FWXFERQ_STREAM ){
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db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST;
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db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST;
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if(mode & FWXFERQ_PACKET ){
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db[db_tr->dbcnt - 1].db.desc.cmd
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db[db_tr->dbcnt - 1].db.desc.control
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|= OHCI_INTERRUPT_ALWAYS;
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}
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}
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db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
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db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS;
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return 1;
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}
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@ -73,7 +73,8 @@ typedef volatile u_int32_t fwohcireg_t;
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struct fwohcidb {
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union {
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struct {
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volatile u_int32_t cmd;
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volatile u_int32_t reqcount:16,
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control:16;
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volatile u_int32_t addr;
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volatile u_int32_t depend;
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volatile u_int32_t count:16,
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@ -81,43 +82,43 @@ struct fwohcidb {
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} desc;
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volatile u_int32_t immed[4];
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} db;
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#define OHCI_OUTPUT_MORE (0 << 28)
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#define OHCI_OUTPUT_LAST (1 << 28)
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#define OHCI_INPUT_MORE (2 << 28)
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#define OHCI_INPUT_LAST (3 << 28)
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#define OHCI_STORE_QUAD (4 << 28)
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#define OHCI_LOAD_QUAD (5 << 28)
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#define OHCI_NOP (6 << 28)
|
||||
#define OHCI_STOP (7 << 28)
|
||||
#define OHCI_STORE (8 << 28)
|
||||
#define OHCI_CMD_MASK (0xf << 28)
|
||||
#define OHCI_OUTPUT_MORE (0 << 12)
|
||||
#define OHCI_OUTPUT_LAST (1 << 12)
|
||||
#define OHCI_INPUT_MORE (2 << 12)
|
||||
#define OHCI_INPUT_LAST (3 << 12)
|
||||
#define OHCI_STORE_QUAD (4 << 12)
|
||||
#define OHCI_LOAD_QUAD (5 << 12)
|
||||
#define OHCI_NOP (6 << 12)
|
||||
#define OHCI_STOP (7 << 12)
|
||||
#define OHCI_STORE (8 << 12)
|
||||
#define OHCI_CMD_MASK (0xf << 12)
|
||||
|
||||
#define OHCI_UPDATE (1 << 27)
|
||||
#define OHCI_UPDATE (1 << 11)
|
||||
|
||||
#define OHCI_KEY_ST0 (0 << 24)
|
||||
#define OHCI_KEY_ST1 (1 << 24)
|
||||
#define OHCI_KEY_ST2 (2 << 24)
|
||||
#define OHCI_KEY_ST3 (3 << 24)
|
||||
#define OHCI_KEY_REGS (5 << 24)
|
||||
#define OHCI_KEY_SYS (6 << 24)
|
||||
#define OHCI_KEY_DEVICE (7 << 24)
|
||||
#define OHCI_KEY_MASK (7 << 24)
|
||||
#define OHCI_KEY_ST0 (0 << 8)
|
||||
#define OHCI_KEY_ST1 (1 << 8)
|
||||
#define OHCI_KEY_ST2 (2 << 8)
|
||||
#define OHCI_KEY_ST3 (3 << 8)
|
||||
#define OHCI_KEY_REGS (5 << 8)
|
||||
#define OHCI_KEY_SYS (6 << 8)
|
||||
#define OHCI_KEY_DEVICE (7 << 8)
|
||||
#define OHCI_KEY_MASK (7 << 8)
|
||||
|
||||
#define OHCI_INTERRUPT_NEVER (0 << 20)
|
||||
#define OHCI_INTERRUPT_TRUE (1 << 20)
|
||||
#define OHCI_INTERRUPT_FALSE (2 << 20)
|
||||
#define OHCI_INTERRUPT_ALWAYS (3 << 20)
|
||||
#define OHCI_INTERRUPT_NEVER (0 << 4)
|
||||
#define OHCI_INTERRUPT_TRUE (1 << 4)
|
||||
#define OHCI_INTERRUPT_FALSE (2 << 4)
|
||||
#define OHCI_INTERRUPT_ALWAYS (3 << 4)
|
||||
|
||||
#define OHCI_BRANCH_NEVER (0 << 18)
|
||||
#define OHCI_BRANCH_TRUE (1 << 18)
|
||||
#define OHCI_BRANCH_FALSE (2 << 18)
|
||||
#define OHCI_BRANCH_ALWAYS (3 << 18)
|
||||
#define OHCI_BRANCH_MASK (3 << 18)
|
||||
#define OHCI_BRANCH_NEVER (0 << 2)
|
||||
#define OHCI_BRANCH_TRUE (1 << 2)
|
||||
#define OHCI_BRANCH_FALSE (2 << 2)
|
||||
#define OHCI_BRANCH_ALWAYS (3 << 2)
|
||||
#define OHCI_BRANCH_MASK (3 << 2)
|
||||
|
||||
#define OHCI_WAIT_NEVER (0 << 16)
|
||||
#define OHCI_WAIT_TRUE (1 << 16)
|
||||
#define OHCI_WAIT_FALSE (2 << 16)
|
||||
#define OHCI_WAIT_ALWAYS (3 << 16)
|
||||
#define OHCI_WAIT_NEVER (0)
|
||||
#define OHCI_WAIT_TRUE (1)
|
||||
#define OHCI_WAIT_FALSE (2)
|
||||
#define OHCI_WAIT_ALWAYS (3)
|
||||
};
|
||||
|
||||
#define OHCI_SPD_S100 0x4
|
||||
|
Loading…
Reference in New Issue
Block a user