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On PowerPC the clock for the BRG comes from RTxC, not PCLK. Add a

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quick hack to deal with this. We may need to formalize this better
and have this information come from the bus attachments.
This commit is contained in:
Marcel Moolenaar 2006-07-26 17:29:37 +00:00
parent afd396ac93
commit 54cfafcf98
1 changed files with 10 additions and 3 deletions
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13
sys/dev/uart/uart_dev_z8530.c
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@ -43,6 +43,13 @@ __FBSDID("$FreeBSD$");
#define DEFAULT_RCLK 307200
/* Hack! */
#ifdef __powerpc__
#define UART_PCLK 0
#else
#define UART_PCLK MCB2_PCLK
#endif
/* Multiplexed I/O. */
static __inline void
uart_setmreg(struct uart_bas *bas, int reg, int val)
@ -124,7 +131,7 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
} else
divisor = -1;
uart_setmreg(bas, WR_MCB2, MCB2_PCLK);
uart_setmreg(bas, WR_MCB2, UART_PCLK);
uart_barrier(bas);
if (divisor >= 0) {
@ -140,7 +147,7 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
uart_barrier(bas);
uart_setmreg(bas, WR_TPC, tpc);
uart_barrier(bas);
uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE);
uart_barrier(bas);
*tpcp = tpc;
return (0);
@ -167,7 +174,7 @@ z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
uart_barrier(bas);
/* Set clock sources. */
uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
uart_setmreg(bas, WR_MCB2, MCB2_PCLK);
uart_setmreg(bas, WR_MCB2, UART_PCLK);
uart_barrier(bas);
/* Set data encoding. */
uart_setmreg(bas, WR_MCB1, MCB1_NRZ);