o Add support for multi-port instances of Synopsys DesignWare APB GPIO
Controller. o Rename the driver to dwgpio. Sponsored by: DARPA, AFRL
This commit is contained in:
parent
1f6453b126
commit
564e82561b
sys
@ -5,7 +5,6 @@ arm/altera/socfpga/socfpga_machdep.c standard
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arm/altera/socfpga/socfpga_manager.c standard
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arm/altera/socfpga/socfpga_rstmgr.c standard
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arm/altera/socfpga/socfpga_mp.c optional smp
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arm/altera/socfpga/socfpga_gpio.c optional gpio
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dev/mmc/host/dwmmc.c optional dwmmc
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dev/mmc/host/dwmmc_altera.c optional dwmmc
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015, 2019 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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@ -29,15 +29,12 @@
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*/
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/*
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* SOCFPGA General-Purpose I/O Interface.
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* Synopsys® DesignWare® APB General Purpose Programming I/O
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* (DW_apb_gpio) peripheral.
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*
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* Chapter 22, Cyclone V Device Handbook (CV-5V2 2014.07.22)
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*/
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/*
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* The GPIO modules are instances of the Synopsys® DesignWare® APB General
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* Purpose Programming I/O (DW_apb_gpio) peripheral.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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@ -53,6 +50,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/watchdog.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <sys/reboot.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/openfirm.h>
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@ -64,14 +62,13 @@ __FBSDID("$FreeBSD$");
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#include <machine/intr.h>
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#include "gpio_if.h"
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#include "dwgpio_if.h"
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#define READ4(_sc, _reg) \
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bus_read_4((_sc)->res[0], _reg)
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#define WRITE4(_sc, _reg, _val) \
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bus_write_4((_sc)->res[0], _reg, _val)
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#define READ4(_sc, _reg) DWGPIO_READ((_sc)->parent, _reg)
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#define WRITE4(_sc, _reg, _val) DWGPIO_WRITE((_sc)->parent, _reg, _val)
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#define GPIO_SWPORTA_DR 0x00 /* Port A Data Register */
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#define GPIO_SWPORTA_DDR 0x04 /* Port A Data Direction Register */
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#define GPIO_SWPORT_DR(n) (0x00 + 0xc * (n)) /* Port n Data Register */
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#define GPIO_SWPORT_DDR(n) (0x04 + 0xc * (n)) /* Port n Data Direction */
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#define GPIO_INTEN 0x30 /* Interrupt Enable Register */
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#define GPIO_INTMASK 0x34 /* Interrupt Mask Register */
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#define GPIO_INTTYPE_LEVEL 0x38 /* Interrupt Level Register */
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@ -80,7 +77,7 @@ __FBSDID("$FreeBSD$");
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#define GPIO_RAW_INTSTATUS 0x44 /* Raw Interrupt Status Register */
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#define GPIO_DEBOUNCE 0x48 /* Debounce Enable Register */
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#define GPIO_PORTA_EOI 0x4C /* Clear Interrupt Register */
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#define GPIO_EXT_PORTA 0x50 /* External Port A Register */
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#define GPIO_EXT_PORT(n) (0x50 + 0x4 * (n)) /* External Port n */
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#define GPIO_LS_SYNC 0x60 /* Synchronization Level Register */
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#define GPIO_ID_CODE 0x64 /* ID Code Register */
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#define GPIO_VER_ID_CODE 0x6C /* GPIO Version Register */
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@ -89,13 +86,6 @@ __FBSDID("$FreeBSD$");
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#define ENCODED_ID_PWIDTH_S(n) (5 * n) /* Width of GPIO Port N Shift */
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#define GPIO_CONFIG_REG1 0x74 /* Configuration Register 1 */
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enum port_no {
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PORTA,
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PORTB,
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PORTC,
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PORTD,
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};
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#define NR_GPIO_MAX 32 /* Maximum pins per port */
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#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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@ -106,43 +96,35 @@ enum port_no {
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/*
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* GPIO interface
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*/
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static device_t socfpga_gpio_get_bus(device_t);
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static int socfpga_gpio_pin_max(device_t, int *);
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static int socfpga_gpio_pin_getcaps(device_t, uint32_t, uint32_t *);
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static int socfpga_gpio_pin_getname(device_t, uint32_t, char *);
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static int socfpga_gpio_pin_getflags(device_t, uint32_t, uint32_t *);
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static int socfpga_gpio_pin_setflags(device_t, uint32_t, uint32_t);
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static int socfpga_gpio_pin_set(device_t, uint32_t, unsigned int);
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static int socfpga_gpio_pin_get(device_t, uint32_t, unsigned int *);
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static int socfpga_gpio_pin_toggle(device_t, uint32_t pin);
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struct socfpga_gpio_softc {
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struct resource *res[1];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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static device_t dwgpio_get_bus(device_t);
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static int dwgpio_pin_max(device_t, int *);
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static int dwgpio_pin_getcaps(device_t, uint32_t, uint32_t *);
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static int dwgpio_pin_getname(device_t, uint32_t, char *);
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static int dwgpio_pin_getflags(device_t, uint32_t, uint32_t *);
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static int dwgpio_pin_setflags(device_t, uint32_t, uint32_t);
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static int dwgpio_pin_set(device_t, uint32_t, unsigned int);
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static int dwgpio_pin_get(device_t, uint32_t, unsigned int *);
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static int dwgpio_pin_toggle(device_t, uint32_t pin);
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struct dwgpio_softc {
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device_t dev;
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device_t busdev;
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device_t parent;
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struct mtx sc_mtx;
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int gpio_npins;
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struct gpio_pin gpio_pins[NR_GPIO_MAX];
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};
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struct socfpga_gpio_softc *gpio_sc;
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static struct resource_spec socfpga_gpio_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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phandle_t node;
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int port;
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};
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static int
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socfpga_gpio_probe(device_t dev)
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dwgpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio"))
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if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio-port"))
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return (ENXIO);
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device_set_desc(dev, "DesignWare General-Purpose I/O Interface");
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@ -150,41 +132,32 @@ socfpga_gpio_probe(device_t dev)
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}
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static int
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socfpga_gpio_attach(device_t dev)
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dwgpio_attach(device_t dev)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int version;
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int nr_pins;
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int cfg2;
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int i;
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sc = device_get_softc(dev);
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sc->parent = device_get_parent(dev);
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sc->node = ofw_bus_get_node(dev);
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sc->dev = dev;
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mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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if (bus_alloc_resources(dev, socfpga_gpio_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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mtx_destroy(&sc->sc_mtx);
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if ((OF_getencprop(sc->node, "reg", &sc->port, sizeof(sc->port))) <= 0)
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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gpio_sc = sc;
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printf("port %d\n", sc->port);
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version = READ4(sc, GPIO_VER_ID_CODE);
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#if 0
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device_printf(sc->dev, "Version = 0x%08x\n", version);
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#endif
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if (boothowto & RB_VERBOSE)
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device_printf(sc->dev, "Version = 0x%08x\n", version);
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/*
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* Take number of pins from hardware.
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* XXX: Assume we have GPIO port A only.
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*/
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/* Grab number of pins from hardware. */
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cfg2 = READ4(sc, GPIO_CONFIG_REG2);
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nr_pins = (cfg2 >> ENCODED_ID_PWIDTH_S(PORTA)) & \
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nr_pins = (cfg2 >> ENCODED_ID_PWIDTH_S(sc->port)) & \
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ENCODED_ID_PWIDTH_M;
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sc->gpio_npins = nr_pins + 1;
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@ -192,14 +165,13 @@ socfpga_gpio_attach(device_t dev)
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sc->gpio_pins[i].gp_pin = i;
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sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
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sc->gpio_pins[i].gp_flags =
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(READ4(sc, GPIO_SWPORTA_DDR) & (1 << i)) ?
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(READ4(sc, GPIO_SWPORT_DDR(sc->port)) & (1 << i)) ?
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GPIO_PIN_OUTPUT: GPIO_PIN_INPUT;
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snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
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"socfpga_gpio%d.%d", device_get_unit(dev), i);
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"dwgpio%d.%d", device_get_unit(dev), i);
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}
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sc->busdev = gpiobus_attach_bus(dev);
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if (sc->busdev == NULL) {
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bus_release_resources(dev, socfpga_gpio_spec, sc->res);
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mtx_destroy(&sc->sc_mtx);
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return (ENXIO);
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}
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@ -208,9 +180,9 @@ socfpga_gpio_attach(device_t dev)
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}
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static device_t
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socfpga_gpio_get_bus(device_t dev)
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dwgpio_get_bus(device_t dev)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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sc = device_get_softc(dev);
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@ -218,9 +190,9 @@ socfpga_gpio_get_bus(device_t dev)
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}
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static int
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socfpga_gpio_pin_max(device_t dev, int *maxpin)
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dwgpio_pin_max(device_t dev, int *maxpin)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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sc = device_get_softc(dev);
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@ -230,9 +202,9 @@ socfpga_gpio_pin_max(device_t dev, int *maxpin)
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}
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static int
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socfpga_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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dwgpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int i;
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sc = device_get_softc(dev);
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@ -252,9 +224,9 @@ socfpga_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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}
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static int
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socfpga_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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dwgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int i;
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sc = device_get_softc(dev);
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@ -274,9 +246,9 @@ socfpga_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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}
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static int
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socfpga_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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dwgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int i;
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sc = device_get_softc(dev);
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@ -296,9 +268,9 @@ socfpga_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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}
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static int
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socfpga_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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dwgpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int i;
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sc = device_get_softc(dev);
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@ -311,16 +283,16 @@ socfpga_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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return (EINVAL);
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GPIO_LOCK(sc);
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*val = (READ4(sc, GPIO_EXT_PORTA) & (1 << i)) ? 1 : 0;
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*val = (READ4(sc, GPIO_EXT_PORT(sc->port)) & (1 << i)) ? 1 : 0;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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socfpga_gpio_pin_toggle(device_t dev, uint32_t pin)
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dwgpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int reg;
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int i;
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@ -334,12 +306,12 @@ socfpga_gpio_pin_toggle(device_t dev, uint32_t pin)
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return (EINVAL);
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GPIO_LOCK(sc);
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reg = READ4(sc, GPIO_SWPORTA_DR);
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reg = READ4(sc, GPIO_SWPORT_DR(sc->port));
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if (reg & (1 << i))
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reg &= ~(1 << i);
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else
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reg |= (1 << i);
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WRITE4(sc, GPIO_SWPORTA_DR, reg);
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WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);
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GPIO_UNLOCK(sc);
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return (0);
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@ -347,7 +319,7 @@ socfpga_gpio_pin_toggle(device_t dev, uint32_t pin)
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static void
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socfpga_gpio_pin_configure(struct socfpga_gpio_softc *sc,
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dwgpio_pin_configure(struct dwgpio_softc *sc,
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struct gpio_pin *pin, unsigned int flags)
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{
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int reg;
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@ -358,7 +330,7 @@ socfpga_gpio_pin_configure(struct socfpga_gpio_softc *sc,
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* Manage input/output
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*/
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reg = READ4(sc, GPIO_SWPORTA_DDR);
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reg = READ4(sc, GPIO_SWPORT_DDR(sc->port));
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if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
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pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
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if (flags & GPIO_PIN_OUTPUT) {
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@ -370,15 +342,15 @@ socfpga_gpio_pin_configure(struct socfpga_gpio_softc *sc,
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}
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}
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WRITE4(sc, GPIO_SWPORTA_DDR, reg);
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WRITE4(sc, GPIO_SWPORT_DDR(sc->port), reg);
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GPIO_UNLOCK(sc);
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}
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static int
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socfpga_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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dwgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int i;
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sc = device_get_softc(dev);
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@ -390,15 +362,15 @@ socfpga_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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if (i >= sc->gpio_npins)
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return (EINVAL);
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socfpga_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
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dwgpio_pin_configure(sc, &sc->gpio_pins[i], flags);
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return (0);
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}
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static int
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socfpga_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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dwgpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct socfpga_gpio_softc *sc;
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struct dwgpio_softc *sc;
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int reg;
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int i;
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@ -413,41 +385,41 @@ socfpga_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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return (EINVAL);
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GPIO_LOCK(sc);
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reg = READ4(sc, GPIO_SWPORTA_DR);
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reg = READ4(sc, GPIO_SWPORT_DR(sc->port));
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if (value)
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reg |= (1 << i);
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else
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reg &= ~(1 << i);
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WRITE4(sc, GPIO_SWPORTA_DR, reg);
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WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static device_method_t socfpga_gpio_methods[] = {
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DEVMETHOD(device_probe, socfpga_gpio_probe),
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DEVMETHOD(device_attach, socfpga_gpio_attach),
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static device_method_t dwgpio_methods[] = {
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DEVMETHOD(device_probe, dwgpio_probe),
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DEVMETHOD(device_attach, dwgpio_attach),
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/* GPIO protocol */
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DEVMETHOD(gpio_get_bus, socfpga_gpio_get_bus),
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DEVMETHOD(gpio_pin_max, socfpga_gpio_pin_max),
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DEVMETHOD(gpio_pin_getname, socfpga_gpio_pin_getname),
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DEVMETHOD(gpio_pin_getcaps, socfpga_gpio_pin_getcaps),
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DEVMETHOD(gpio_pin_getflags, socfpga_gpio_pin_getflags),
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DEVMETHOD(gpio_pin_get, socfpga_gpio_pin_get),
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DEVMETHOD(gpio_pin_toggle, socfpga_gpio_pin_toggle),
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DEVMETHOD(gpio_pin_setflags, socfpga_gpio_pin_setflags),
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DEVMETHOD(gpio_pin_set, socfpga_gpio_pin_set),
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DEVMETHOD(gpio_get_bus, dwgpio_get_bus),
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DEVMETHOD(gpio_pin_max, dwgpio_pin_max),
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DEVMETHOD(gpio_pin_getname, dwgpio_pin_getname),
|
||||
DEVMETHOD(gpio_pin_getcaps, dwgpio_pin_getcaps),
|
||||
DEVMETHOD(gpio_pin_getflags, dwgpio_pin_getflags),
|
||||
DEVMETHOD(gpio_pin_get, dwgpio_pin_get),
|
||||
DEVMETHOD(gpio_pin_toggle, dwgpio_pin_toggle),
|
||||
DEVMETHOD(gpio_pin_setflags, dwgpio_pin_setflags),
|
||||
DEVMETHOD(gpio_pin_set, dwgpio_pin_set),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t socfpga_gpio_driver = {
|
||||
static driver_t dwgpio_driver = {
|
||||
"gpio",
|
||||
socfpga_gpio_methods,
|
||||
sizeof(struct socfpga_gpio_softc),
|
||||
dwgpio_methods,
|
||||
sizeof(struct dwgpio_softc),
|
||||
};
|
||||
|
||||
static devclass_t socfpga_gpio_devclass;
|
||||
static devclass_t dwgpio_devclass;
|
||||
|
||||
DRIVER_MODULE(socfpga_gpio, simplebus, socfpga_gpio_driver,
|
||||
socfpga_gpio_devclass, 0, 0);
|
||||
DRIVER_MODULE(dwgpio, dwgpiobus, dwgpio_driver,
|
||||
dwgpio_devclass, 0, 0);
|
166
sys/dev/gpio/dwgpio/dwgpio_bus.c
Normal file
166
sys/dev/gpio/dwgpio/dwgpio_bus.c
Normal file
@ -0,0 +1,166 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory (Department of Computer Science and
|
||||
* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
|
||||
* DARPA SSITH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/rman.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/fdt/simplebus.h>
|
||||
#include <dev/fdt/fdt_common.h>
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include "dwgpio_if.h"
|
||||
|
||||
struct dwgpiobus_softc {
|
||||
struct simplebus_softc simplebus_sc;
|
||||
device_t dev;
|
||||
struct resource *res[1];
|
||||
};
|
||||
|
||||
static struct resource_spec dwgpio_spec[] = {
|
||||
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
|
||||
{ -1, 0 }
|
||||
};
|
||||
|
||||
static int
|
||||
dwgpiobus_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio"))
|
||||
return (ENXIO);
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "Synopsys® DesignWare® APB GPIO BUS");
|
||||
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static int
|
||||
dwgpiobus_attach(device_t dev)
|
||||
{
|
||||
struct dwgpiobus_softc *sc;
|
||||
phandle_t node;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
sc->dev = dev;
|
||||
|
||||
node = ofw_bus_get_node(dev);
|
||||
if (node == -1)
|
||||
return (ENXIO);
|
||||
|
||||
if (bus_alloc_resources(dev, dwgpio_spec, sc->res)) {
|
||||
device_printf(dev, "Could not allocate resources.\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
simplebus_init(dev, node);
|
||||
|
||||
/*
|
||||
* Allow devices to identify.
|
||||
*/
|
||||
bus_generic_probe(dev);
|
||||
|
||||
/*
|
||||
* Now walk the OFW tree and attach top-level devices.
|
||||
*/
|
||||
for (node = OF_child(node); node > 0; node = OF_peer(node))
|
||||
simplebus_add_device(dev, node, 0, NULL, -1, NULL);
|
||||
|
||||
return (bus_generic_attach(dev));
|
||||
}
|
||||
|
||||
static int
|
||||
dwgpiobus_detach(device_t dev)
|
||||
{
|
||||
struct dwgpiobus_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
bus_release_resources(dev, dwgpio_spec, sc->res);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
dwgpiobus_write(device_t dev, bus_size_t offset, int val)
|
||||
{
|
||||
struct dwgpiobus_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
bus_write_4(sc->res[0], offset, val);
|
||||
|
||||
return (0);
|
||||
};
|
||||
|
||||
static int
|
||||
dwgpiobus_read(device_t dev, bus_size_t offset)
|
||||
{
|
||||
struct dwgpiobus_softc *sc;
|
||||
int val;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
val = bus_read_4(sc->res[0], offset);
|
||||
|
||||
return (val);
|
||||
};
|
||||
|
||||
static device_method_t dwgpiobus_methods[] = {
|
||||
DEVMETHOD(device_probe, dwgpiobus_probe),
|
||||
DEVMETHOD(device_attach, dwgpiobus_attach),
|
||||
DEVMETHOD(device_detach, dwgpiobus_detach),
|
||||
|
||||
DEVMETHOD(dwgpio_write, dwgpiobus_write),
|
||||
DEVMETHOD(dwgpio_read, dwgpiobus_read),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
DEFINE_CLASS_1(dwgpiobus, dwgpiobus_driver, dwgpiobus_methods,
|
||||
sizeof(struct dwgpiobus_softc), simplebus_driver);
|
||||
|
||||
static devclass_t dwgpiobus_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(dwgpiobus, simplebus, dwgpiobus_driver, dwgpiobus_devclass,
|
||||
0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|
||||
MODULE_VERSION(dwgpiobus, 1);
|
52
sys/dev/gpio/dwgpio/dwgpio_if.m
Normal file
52
sys/dev/gpio/dwgpio/dwgpio_if.m
Normal file
@ -0,0 +1,52 @@
|
||||
#-
|
||||
# Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
|
||||
#
|
||||
# This software was developed by SRI International and the University of
|
||||
# Cambridge Computer Laboratory (Department of Computer Science and
|
||||
# Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
|
||||
# DARPA SSITH research programme.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
# SUCH DAMAGE.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
INTERFACE dwgpio;
|
||||
|
||||
#
|
||||
# GPIO write
|
||||
#
|
||||
METHOD int write {
|
||||
device_t dev;
|
||||
bus_size_t offset;
|
||||
int val;
|
||||
};
|
||||
|
||||
#
|
||||
# GPIO read
|
||||
#
|
||||
METHOD int read {
|
||||
device_t dev;
|
||||
bus_size_t offset;
|
||||
};
|
Loading…
x
Reference in New Issue
Block a user