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Bring over some further HAL capabilities from the Atheros HAL, as well

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as an EDMA check function.

For the AR9003 and later NICs, different TX/RX DMA and descriptor handling
code will be conditional on the EDMA check.

Obtained from:	Qualcomm Atheros
This commit is contained in:
Adrian Chadd 2012-07-02 06:02:12 +00:00
parent 6959b14df6
commit 577cd9a9b2
2 changed files with 26 additions and 2 deletions
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25
sys/dev/ath/ath_hal/ah.h
View File

@ -110,7 +110,7 @@ typedef enum {
HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
HAL_CAP_PCIE_PS = 29,
HAL_CAP_HT = 30, /* hardware can support HT */
HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */
HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */
@ -120,6 +120,9 @@ typedef enum {
HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
HAL_CAP_RIFS_RX = 39,
HAL_CAP_RIFS_TX = 40,
HAL_CAP_FORCE_PPM = 41,
HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
HAL_CAP_DFS_DMN = 44, /* current DFS domain */
@ -131,8 +134,27 @@ typedef enum {
HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */
HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */
HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
HAL_CAP_BB_RIFS_HANG = 52,
HAL_CAP_RIFS_RX_ENABLED = 53,
HAL_CAP_BB_DFS_HANG = 54,
HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */
HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */
HAL_CAP_DS = 67, /* 2 stream */
HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68,
HAL_CAP_MAC_HANG = 69, /* can MAC hang */
HAL_CAP_MFP = 70, /* Manangement Frame Protection in hardware */
HAL_CAP_TS = 72, /* 3 stream */
HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */
HAL_CAP_RX_BUFSIZE = 81,
HAL_CAP_NUM_MR_ENTRIES = 82,
HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */
HAL_CAP_BB_PANIC_WATCHDOG = 92,
HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
@ -144,7 +166,6 @@ typedef enum {
HAL_CAP_INTMIT = 229, /* interference mitigation */
HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
HAL_CAP_BB_HANG = 235, /* can baseband hang */
HAL_CAP_MAC_HANG = 236, /* can MAC hang */
HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */

3
sys/dev/ath/if_athvar.h
View File

@ -942,6 +942,9 @@ void ath_intr(void *);
#define ath_hal_setintmit(_ah, _v) \
ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \
HAL_CAP_INTMIT_ENABLE, _v, NULL)
#define ath_hal_hasedma(_ah) \
(ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \
0, NULL) == HAL_OK)
#define ath_hal_getchannoise(_ah, _c) \
((*(_ah)->ah_getChanNoise)((_ah), (_c)))
#define ath_hal_getrxchainmask(_ah, _prxchainmask) \