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Import some HOWL (AR9130) related fixes from Atheros.

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Obtained from:	Atheros
This commit is contained in:
Adrian Chadd 2011-05-05 02:59:31 +00:00
parent 489eeba940
commit 59298273a9
2 changed files with 30 additions and 2 deletions
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26
sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
View File

@ -251,7 +251,12 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
/* Restore previous led state */
OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState);
if (AR_SREV_HOWL(ah))
OS_REG_WRITE(ah, AR_MAC_LED,
AR_MAC_LED_ASSOC_ACTIVE | AR_CFG_SCLK_32KHZ);
else
OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) |
saveLedState);
/* Restore previous antenna */
OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
@ -332,6 +337,19 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
if (AR_SREV_HOWL(ah)) {
/*
* Enable the MBSSID block-ack fix for HOWL.
* This feature is only supported on Howl 1.4, but it is safe to
* set bit 22 of STA_ID1 on other Howl revisions (1.1, 1.2, 1.3),
* since bit 22 is unused in those Howl revisions.
*/
unsigned int reg;
reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22));
OS_REG_WRITE(ah,AR_STA_ID1, reg);
ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg);
}
HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
OS_MARK(ah, AH_MARK_RESET_DONE, 0);
@ -1205,7 +1223,11 @@ ar5416SetReset(struct ath_hal *ah, int type)
#endif /* AH_SUPPORT_AR9130 */
OS_REG_WRITE(ah, AR_RTC_RC, rst_flags);
OS_DELAY(50);
if (AR_SREV_HOWL(ah))
OS_DELAY(10000);
else
OS_DELAY(100);
/*
* Clear resets and force wakeup

6
sys/dev/ath/ath_hal/ar5416/ar5416reg.h
View File

@ -199,6 +199,12 @@
#define AR_RXCFG_DMASZ_512B 7
/* MAC Led registers */
#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */
#define AR_CFG_SCLK_RATE_IND_S 0
#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */
#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */
#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */
#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */
#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */
#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */
#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */