aic7xxx: minor spelling fixes.
Affects mostly comments but also a visible text string, Differential Revision: https://reviews.freebsd.org/D6270
This commit is contained in:
parent
ae14b49908
commit
594c945a54
@ -1206,7 +1206,7 @@ ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
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* that requires host assistance for completion.
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* While handling the message phase(s), we will be
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* notified by the sequencer after each byte is
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* transfered so we can track bus phase changes.
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* transferred so we can track bus phase changes.
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*
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* If this is the first time we've seen a HOST_MSG_LOOP
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* interrupt, initialize the state of the host message
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@ -1620,7 +1620,7 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
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/*
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* Although the driver does not care about the
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* 'Selection in Progress' status bit, the busy
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* LED does. SELINGO is only cleared by a sucessfull
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* LED does. SELINGO is only cleared by a successful
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* selection, so we must manually clear it to insure
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* the LED turns off just incase no future successful
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* selections occur (e.g. no devices on the bus).
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@ -2695,7 +2695,7 @@ ahd_clear_critical_section(struct ahd_softc *ahd)
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ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
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ahd_outb(ahd, SIMODE1, simode1);
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/*
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* SCSIINT seems to glitch occassionally when
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* SCSIINT seems to glitch occasionally when
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* the interrupt masks are restored. Clear SCSIINT
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* one more time so that only persistent errors
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* are seen as a real interrupt.
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@ -3023,7 +3023,7 @@ ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
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/*
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* Update the bitmask of targets for which the controller should
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* negotiate with at the next convenient oportunity. This currently
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* negotiate with at the next convenient opportunity. This currently
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* means the next time we send the initial identify messages for
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* a new transaction.
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*/
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@ -3374,7 +3374,7 @@ ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
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/*
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* During packetized transfers, the target will
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* give us the oportunity to send command packets
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* give us the opportunity to send command packets
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* without us asserting attention.
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*/
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if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
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@ -4838,7 +4838,7 @@ ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
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/*
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* Requeue all tagged commands for this target
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* currently in our posession so they can be
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* currently in our possession so they can be
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* converted to untagged commands.
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*/
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ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
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@ -5489,7 +5489,7 @@ ahd_shutdown(void *arg)
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/*
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* Reset the controller and record some information about it
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* that is only available just after a reset. If "reinit" is
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* non-zero, this reset occured after initial configuration
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* non-zero, this reset occurred after initial configuration
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* and the caller requests that the chip be fully reinitialized
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* to a runable state. Chip interrupts are *not* enabled after
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* a reinitialization. The caller must enable interrupts via
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@ -5742,7 +5742,7 @@ ahd_init_scbdata(struct ahd_softc *ahd)
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}
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/*
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* Note that we were successfull
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* Note that we were successful
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*/
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return (0);
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@ -8785,7 +8785,7 @@ ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
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cur_patch += cur_patch->skip_patch;
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} else {
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/* Accepted this patch. Advance to the next
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* one and wait for our intruction pointer to
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* one and wait for our instruction pointer to
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* hit this point.
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*/
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cur_patch++;
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@ -9664,7 +9664,7 @@ ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
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return (error);
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/*
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* Write the data. If we don't get throught the loop at
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* Write the data. If we don't get through the loop at
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* least once, the arguments were invalid.
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*/
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retval = EINVAL;
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@ -478,7 +478,7 @@ struct hardware_scb {
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* each S/G element is expired, its datacnt field is checked to see
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* if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
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* residual sg ptr and the transfer is considered complete. If the
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* sequencer determines that there is a residual in the tranfer, or
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* sequencer determines that there is a residual in the transfer, or
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* there is non-zero status, it will set the SG_STATUS_VALID flag in
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* sgptr and dma the scb back into host memory. To sumarize:
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*
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@ -486,7 +486,7 @@ struct hardware_scb {
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* o A residual has occurred if SG_FULL_RESID is set in sgptr,
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* or residual_sgptr does not have SG_LIST_NULL set.
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*
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* o We are transfering the last segment if residual_datacnt has
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* o We are transferring the last segment if residual_datacnt has
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* the SG_LAST_SEG flag set.
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*
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* Host:
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@ -529,7 +529,7 @@ struct hardware_scb {
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*/
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/*
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* Definition of a scatter/gather element as transfered to the controller.
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* Definition of a scatter/gather element as transferred to the controller.
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* The aic7xxx chips only support a 24bit length. We use the top byte of
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* the length to store additional address bits and a flag to indicate
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* that a given segment terminates the transfer. This gives us an
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@ -283,7 +283,7 @@ register HS_MAILBOX {
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}
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/*
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* Sequencer Interupt Status
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* Sequencer Interrupt Status
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*/
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register SEQINTSTAT {
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address 0x00C
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@ -643,7 +643,7 @@ register DCHRXMSG0 {
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}
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/*
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* CMC Recieve Message 0
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* CMC Receive Message 0
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*/
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register CMCRXMSG0 {
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address 0x090
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@ -654,7 +654,7 @@ register CMCRXMSG0 {
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}
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/*
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* Overlay Recieve Message 0
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* Overlay Receive Message 0
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*/
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register OVLYRXMSG0 {
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address 0x090
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@ -690,7 +690,7 @@ register DCHRXMSG1 {
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}
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/*
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* CMC Recieve Message 1
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* CMC Receive Message 1
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*/
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register CMCRXMSG1 {
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address 0x091
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@ -700,7 +700,7 @@ register CMCRXMSG1 {
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}
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/*
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* Overlay Recieve Message 1
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* Overlay Receive Message 1
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*/
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register OVLYRXMSG1 {
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address 0x091
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@ -735,7 +735,7 @@ register DCHRXMSG2 {
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}
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/*
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* CMC Recieve Message 2
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* CMC Receive Message 2
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*/
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register CMCRXMSG2 {
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address 0x092
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@ -745,7 +745,7 @@ register CMCRXMSG2 {
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}
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/*
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* Overlay Recieve Message 2
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* Overlay Receive Message 2
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*/
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register OVLYRXMSG2 {
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address 0x092
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@ -774,7 +774,7 @@ register DCHRXMSG3 {
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}
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/*
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* CMC Recieve Message 3
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* CMC Receive Message 3
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*/
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register CMCRXMSG3 {
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address 0x093
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@ -784,7 +784,7 @@ register CMCRXMSG3 {
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}
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/*
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* Overlay Recieve Message 3
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* Overlay Receive Message 3
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*/
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register OVLYRXMSG3 {
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address 0x093
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@ -1192,7 +1192,7 @@ register TARGPCISTAT {
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/*
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* LQ Packet In
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* The last LQ Packet recieved
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* The last LQ Packet received
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*/
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register LQIN {
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address 0x020
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@ -2424,7 +2424,7 @@ register IOPDNCTL {
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}
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/*
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* Shaddow Host Address.
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* Shadow Host Address.
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*/
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register SHADDR {
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address 0x060
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@ -3726,7 +3726,7 @@ scratch_ram {
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/*
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* The maximum amount of time to wait, when interrupt coalescing
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* is enabled, before issueing a CMDCMPLT interrupt for a completed
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* is enabled, before issuing a CMDCMPLT interrupt for a completed
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* command.
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*/
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INT_COALESCING_TIMER {
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@ -217,7 +217,7 @@ BEGIN_CRITICAL;
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scbdma_tohost_done:
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test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
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/*
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* An SCB has been succesfully uploaded to the host.
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* An SCB has been successfully uploaded to the host.
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* If the SCB was uploaded for some reason other than
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* bad SCSI status (currently only for underruns), we
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* queue the SCB for normal completion. Otherwise, we
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@ -960,7 +960,7 @@ p_status_okay:
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* This is done to allow the host to send messages outside of an identify
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* sequence while protecting the seqencer from testing the MK_MESSAGE bit
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* on an SCB that might not be for the current nexus. (For example, a
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* BDR message in responce to a bad reselection would leave us pointed to
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* BDR message in response to a bad reselection would leave us pointed to
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* an SCB that doesn't have anything to do with the current target).
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*
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* Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
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@ -1507,7 +1507,7 @@ service_fifo:
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* If the other FIFO needs loading, then it
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* must not have claimed the S/G cache yet
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* (SG_CACHE_AVAIL would have been cleared in
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* the orginal FIFO mode and we test this above).
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* the original FIFO mode and we test this above).
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* Return to the idle loop so we can process the
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* FIFO not currently on the bus first.
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*/
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@ -1551,7 +1551,7 @@ idle_sg_avail:
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test DFSTATUS, PRELOAD_AVAIL jz return;
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/*
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* On the A, preloading a segment before HDMAENACK
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* comes true can clobber the shaddow address of the
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* comes true can clobber the shadow address of the
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* first segment in the S/G FIFO. Wait until it is
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* safe to proceed.
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*/
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@ -2004,10 +2004,10 @@ pkt_handle_xfer:
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* Defer handling of this NONPACKREQ until we
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* can be sure it pertains to this FIFO. SAVEPTRS
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* will not be asserted if the NONPACKREQ is for us,
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* so we must simulate it if shaddow is valid. If
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* shaddow is not valid, keep running this FIFO until we
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* so we must simulate it if shadow is valid. If
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* shadow is not valid, keep running this FIFO until we
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* have satisfied the transfer by loading segments and
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* waiting for either shaddow valid or last_seg_done.
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* waiting for either shadow valid or last_seg_done.
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*/
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test MDFFSTAT, SHVALID jnz pkt_saveptrs;
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pkt_service_fifo:
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@ -2171,7 +2171,7 @@ pkt_status_check_nonpackreq:
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/*
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* The unexpected nonpkt phase handler assumes that any
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* data channel use will have a FIFO reference count. It
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* turns out that the status handler doesn't need a refernce
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* turns out that the status handler doesn't need a references
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* count since the status received flag, and thus completion
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* processing, cannot be set until the handler is finished.
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* We increment the count here to make the nonpkt handler
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@ -417,7 +417,7 @@ ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
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- (uint8_t *)ahd->qoutfifo);
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}
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/*********************** Miscelaneous Support Functions ***********************/
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/********************** Miscellaneous Support Functions ***********************/
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static __inline void ahd_complete_scb(struct ahd_softc *ahd,
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struct scb *scb);
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static __inline void ahd_update_residual(struct ahd_softc *ahd,
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@ -534,7 +534,7 @@ static __inline void
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ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
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{
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/*
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* Write low byte first to accomodate registers
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* Write low byte first to accommodate registers
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* such as PRGMCNT where the order maters.
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*/
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ahd_outb(ahd, port, value & 0xFF);
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@ -489,7 +489,7 @@ ahd_pci_test_register_access(struct ahd_softc *ahd)
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* Next create a situation where write combining
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* or read prefetching could be initiated by the
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* CPU or host bridge. Our device does not support
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* either, so look for data corruption and/or flaged
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* either, so look for data corruption and/or flagged
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* PCI errors. First pause without causing another
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* chip reset.
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*/
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@ -1011,7 +1011,7 @@ ahd_aic790X_setup(struct ahd_softc *ahd)
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| AHD_FAINT_LED_BUG;
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/*
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* IO Cell paramter setup.
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* IO Cell parameter setup.
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*/
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AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
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@ -1032,7 +1032,7 @@ ahd_aic790X_setup(struct ahd_softc *ahd)
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| AHD_BUSFREEREV_BUG;
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/*
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* IO Cell paramter setup.
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* IO Cell parameter setup.
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*/
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AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
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AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
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@ -116,7 +116,7 @@ static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
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/*
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* Valid SCSIRATE values. (p. 3-17)
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* Provides a mapping of tranfer periods in ns to the proper value to
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* Provides a mapping of transfer periods in ns to the proper value to
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* stick in the scsixfer reg.
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*/
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static struct ahc_syncrate ahc_syncrates[] =
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@ -682,7 +682,7 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
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* that requires host assistance for completion.
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* While handling the message phase(s), we will be
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* notified by the sequencer after each byte is
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* transfered so we can track bus phase changes.
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* transferred so we can track bus phase changes.
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*
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* If this is the first time we've seen a HOST_MSG_LOOP
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* interrupt, initialize the state of the host message
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@ -925,7 +925,7 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
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scbptr, ahc_inb(ahc, ARG_1),
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ahc->scb_data->hscbs[scbptr].tag);
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ahc_dump_card_state(ahc);
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panic("for saftey");
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panic("for safety");
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break;
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}
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case OUT_OF_RANGE:
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@ -1171,7 +1171,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
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/*
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* Although the driver does not care about the
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* 'Selection in Progress' status bit, the busy
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* LED does. SELINGO is only cleared by a sucessfull
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* LED does. SELINGO is only cleared by a successful
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* selection, so we must manually clear it to insure
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* the LED turns off just incase no future successful
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* selections occur (e.g. no devices on the bus).
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@ -1381,7 +1381,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
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if (lastphase != P_BUSFREE) {
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/*
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* Renegotiate with this device at the
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* next oportunity just in case this busfree
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* next opportunity just in case this busfree
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* is due to a negotiation mismatch with the
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* device.
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*/
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@ -1857,7 +1857,7 @@ ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
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/*
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* Update the bitmask of targets for which the controller should
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* negotiate with at the next convenient oportunity. This currently
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* negotiate with at the next convenient opportunity. This currently
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* means the next time we send the initial identify messages for
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* a new transaction.
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*/
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@ -3627,7 +3627,7 @@ ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
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/*
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* Requeue all tagged commands for this target
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* currently in our posession so they can be
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* currently in our possession so they can be
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* converted to untagged commands.
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*/
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ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
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@ -4136,7 +4136,7 @@ ahc_shutdown(void *arg)
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/*
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* Reset the controller and record some information about it
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* that is only available just after a reset. If "reinit" is
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* non-zero, this reset occured after initial configuration
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* non-zero, this reset occurred after initial configuration
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* and the caller requests that the chip be fully reinitialized
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* to a runable state. Chip interrupts are *not* enabled after
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* a reinitialization. The caller must enable interrupts via
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@ -4458,7 +4458,7 @@ ahc_init_scbdata(struct ahc_softc *ahc)
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ahc->next_queued_scb = ahc_get_scb(ahc);
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/*
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* Note that we were successfull
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* Note that we were successful
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*/
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return (0);
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@ -6543,7 +6543,7 @@ ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
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cur_patch += cur_patch->skip_patch;
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} else {
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/* Accepted this patch. Advance to the next
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* one and wait for our intruction pointer to
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* one and wait for our instruction pointer to
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* hit this point.
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*/
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cur_patch++;
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@ -7247,7 +7247,7 @@ bus_reset:
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ahc_outb(ahc, SCBPTR, saved_scbptr);
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aic_scb_timer_reset(scb, 2 * 1000);
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} else {
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/* Go "immediatly" to the bus reset */
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/* Go "immediately" to the bus reset */
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/* This shouldn't happen */
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ahc_set_recoveryscb(ahc, scb);
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ahc_print_path(ahc, scb);
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||||
|
@ -448,7 +448,7 @@ struct hardware_scb {
|
||||
* each S/G element is expired, its datacnt field is checked to see
|
||||
* if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
|
||||
* residual sg ptr and the transfer is considered complete. If the
|
||||
* sequencer determines that there is a residual in the tranfer, it
|
||||
* sequencer determines that there is a residual in the transfer, it
|
||||
* will set the SG_RESID_VALID flag in sgptr and dma the scb back into
|
||||
* host memory. To sumarize:
|
||||
*
|
||||
@ -456,7 +456,7 @@ struct hardware_scb {
|
||||
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
|
||||
* or residual_sgptr does not have SG_LIST_NULL set.
|
||||
*
|
||||
* o We are transfering the last segment if residual_datacnt has
|
||||
* o We are transferring the last segment if residual_datacnt has
|
||||
* the SG_LAST_SEG flag set.
|
||||
*
|
||||
* Host:
|
||||
@ -510,7 +510,7 @@ struct hardware_scb {
|
||||
*/
|
||||
|
||||
/*
|
||||
* Definition of a scatter/gather element as transfered to the controller.
|
||||
* Definition of a scatter/gather element as transferred to the controller.
|
||||
* The aic7xxx chips only support a 24bit length. We use the top byte of
|
||||
* the length to store additional address bits and a flag to indicate
|
||||
* that a given segment terminates the transfer. This gives us an
|
||||
|
@ -329,7 +329,7 @@ register SSTAT2 {
|
||||
address 0x00d
|
||||
access_mode RO
|
||||
field OVERRUN 0x80
|
||||
field SHVALID 0x40 /* Shaddow Layer non-zero */
|
||||
field SHVALID 0x40 /* Shadow Layer non-zero */
|
||||
field EXP_ACTIVE 0x10 /* SCSI Expander Active */
|
||||
field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
|
||||
field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
|
||||
|
@ -60,7 +60,7 @@ PREFIX = "ahc_"
|
||||
* use byte 27 of the SCB as a psuedo-next pointer and to thread a list
|
||||
* of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
|
||||
* SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
|
||||
* this list everytime a request sense occurs or after completing a non-tagged
|
||||
* this list every time a request sense occurs or after completing a non-tagged
|
||||
* command for which a second SCB has been queued. The sequencer will
|
||||
* automatically consume the entries.
|
||||
*/
|
||||
@ -1489,7 +1489,7 @@ p_status_okay:
|
||||
* This is done to allow the host to send messages outside of an identify
|
||||
* sequence while protecting the seqencer from testing the MK_MESSAGE bit
|
||||
* on an SCB that might not be for the current nexus. (For example, a
|
||||
* BDR message in responce to a bad reselection would leave us pointed to
|
||||
* BDR message in response to a bad reselection would leave us pointed to
|
||||
* an SCB that doesn't have anything to do with the current target).
|
||||
*
|
||||
* Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
|
||||
|
@ -229,7 +229,7 @@ ahc_name(struct ahc_softc *ahc)
|
||||
return (ahc->name);
|
||||
}
|
||||
|
||||
/*********************** Miscelaneous Support Functions ***********************/
|
||||
/********************** Miscellaneous Support Functions ***********************/
|
||||
|
||||
static __inline void ahc_update_residual(struct ahc_softc *ahc,
|
||||
struct scb *scb);
|
||||
|
@ -865,7 +865,7 @@ ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
|
||||
ahc->bus_suspend = ahc_pci_suspend;
|
||||
ahc->bus_resume = ahc_pci_resume;
|
||||
|
||||
/* Remeber how the card was setup in case there is no SEEPROM */
|
||||
/* Remember how the card was setup in case there is no SEEPROM */
|
||||
if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
|
||||
ahc_pause(ahc);
|
||||
if ((ahc->features & AHC_ULTRA2) != 0)
|
||||
@ -936,7 +936,7 @@ ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
|
||||
}
|
||||
|
||||
/*
|
||||
* We cannot perform ULTRA speeds without the presense
|
||||
* We cannot perform ULTRA speeds without the presence
|
||||
* of the external precision resistor.
|
||||
*/
|
||||
if ((ahc->features & AHC_ULTRA) != 0) {
|
||||
@ -1054,7 +1054,7 @@ ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
|
||||
}
|
||||
|
||||
/*
|
||||
* Test for the presense of external sram in an
|
||||
* Test for the presence of external sram in an
|
||||
* "unshared" configuration.
|
||||
*/
|
||||
static int
|
||||
|
@ -668,7 +668,7 @@ check_patch(patch_t **start_patch, unsigned int start_instr,
|
||||
cur_patch = STAILQ_NEXT(cur_patch, links);
|
||||
} else {
|
||||
/* Accepted this patch. Advance to the next
|
||||
* one and wait for our intruction pointer to
|
||||
* one and wait for our instruction pointer to
|
||||
* hit this point.
|
||||
*/
|
||||
cur_patch = STAILQ_NEXT(cur_patch, links);
|
||||
|
@ -1286,8 +1286,8 @@ code:
|
||||
;
|
||||
|
||||
/*
|
||||
* This grammer differs from the one in the aic7xxx
|
||||
* reference manual since the grammer listed there is
|
||||
* This grammar differs from the one in the aic7xxx
|
||||
* reference manual since the grammar listed there is
|
||||
* ambiguous and causes a shift/reduce conflict.
|
||||
* It also seems more logical as the "immediate"
|
||||
* argument is listed as the second arg like the
|
||||
@ -1753,7 +1753,7 @@ format_3_instr(int opcode, symbol_ref_t *src,
|
||||
instr = seq_alloc();
|
||||
f3_instr = &instr->format.format3;
|
||||
if (address->symbol == NULL) {
|
||||
/* 'dot' referrence. Use the current instruction pointer */
|
||||
/* 'dot' reference. Use the current instruction pointer */
|
||||
addr = instruction_ptr + address->offset;
|
||||
} else if (address->symbol->type == UNINITIALIZED) {
|
||||
/* forward reference */
|
||||
|
Loading…
x
Reference in New Issue
Block a user