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Do not expose to scheduler caches of single CPU.

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Before this change my dual-Xeon(R) Gold 6242R always reported 3 levels
or topology (root, package/L3 and core/L2).  But with SMT disabled
core/L2 matches thread, so additional topology level only causes more
traversal work.  With this change SMT case is reported same as before,
while non-SMT is reported with only 2 much more simple levels.

MFC after:	2 weeks
This commit is contained in:
Alexander Motin 2021-07-28 16:15:43 -04:00
parent cc55ee8009
commit 5a49f19141
1 changed files with 6 additions and 0 deletions
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6
sys/x86/x86/mp_x86.c
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@ -829,6 +829,12 @@ x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
node = topo_next_nonchild_node(root, node);
}
/*
* We are not interested in nodes including only one CPU each.
*/
if (nchildren == root->cpu_count)
return;
cg_root->cg_child = smp_topo_alloc(nchildren);
cg_root->cg_children = nchildren;