PowerNV: make PowerNV PCIe working on a real hardware
Fixes: - map all devices to PE0 - use 1:1 TCE mapping - provide the same TCE mapping for all PEs (not only PE0) - add TCE reset and alignment (required by OPAL) Created by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: QCM Technologies
This commit is contained in:
Wojciech Macek
parent
957fc241ec
commit
5c3e53ef19
@ -65,10 +65,13 @@ int opal_call(uint64_t token, ...);
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#define OPAL_GET_MSI_32 39
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#define OPAL_GET_MSI_64 40
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#define OPAL_PCI_MSI_EOI 63
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#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
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#define OPAL_START_CPU 41
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#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
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#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
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#define OPAL_RETURN_CPU 69
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#define OPAL_REINIT_CPUS 70
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#define OPAL_PCI_TCE_KILL 126
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/* For OPAL_PCI_SET_PE */
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#define OPAL_UNMAP_PE 0
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@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2015-2016 Nathan Whitehorn
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* Copyright (c) 2017-2018 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -58,6 +59,12 @@ __FBSDID("$FreeBSD$");
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#include "iommu_if.h"
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#include "opal.h"
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#define OPAL_PCI_TCE_MAX_ENTRIES (1024*1024UL)
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#define OPAL_PCI_TCE_SEG_SIZE (16*1024*1024UL)
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#define OPAL_PCI_TCE_R (1UL << 0)
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#define OPAL_PCI_TCE_W (1UL << 1)
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#define PHB3_TCE_KILL_INVAL_ALL (1UL << 63)
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/*
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* Device interface.
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*/
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@ -148,6 +155,8 @@ struct opalpci_softc {
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vmem_t *msi_vmem;
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int msi_base; /* Base XIVE number */
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int base_msi_irq; /* Base IRQ assigned by FreeBSD to this PIC */
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uint64_t *tce; /* TCE table for 1:1 mapping */
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struct resource *r_reg;
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};
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static devclass_t opalpci_devclass;
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@ -177,12 +186,24 @@ opalpci_probe(device_t dev)
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return (BUS_PROBE_GENERIC);
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}
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static void
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pci_phb3_tce_invalidate_entire(struct opalpci_softc *sc)
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{
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mb();
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bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL);
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mb();
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}
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static int
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opalpci_attach(device_t dev)
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{
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struct opalpci_softc *sc;
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cell_t id[2], m64window[6], npe;
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int i, err;
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uint64_t maxmem;
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uint64_t entries;
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int rid;
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sc = device_get_softc(dev);
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@ -204,6 +225,15 @@ opalpci_attach(device_t dev)
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if (bootverbose)
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device_printf(dev, "OPAL ID %#lx\n", sc->phb_id);
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rid = 0;
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sc->r_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&rid, RF_ACTIVE | RF_SHAREABLE);
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if (sc->r_reg == NULL) {
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device_printf(dev, "Failed to allocate PHB[%jd] registers\n",
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(uintmax_t)sc->phb_id);
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return (ENXIO);
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}
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/*
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* Reset PCI IODA table
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*/
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@ -214,46 +244,11 @@ opalpci_attach(device_t dev)
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return (ENXIO);
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}
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while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0)
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DELAY(1000*err); /* Returns expected delay in ms */
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DELAY(1000*(err + 1)); /* Returns expected delay in ms */
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if (err < 0) {
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device_printf(dev, "PHB IODA reset poll failed: %d\n", err);
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return (ENXIO);
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device_printf(dev, "WARNING: PHB IODA reset poll failed: %d\n", err);
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}
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/*
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* Reset everything. Especially important if we have inherited the
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* system from Linux by kexec()
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*/
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#ifdef NOTYET
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if (bootverbose)
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device_printf(dev, "Resetting PCI bus\n");
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err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 1);
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if (err < 0) {
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device_printf(dev, "PHB reset failed: %d\n", err);
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return (ENXIO);
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}
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while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0)
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DELAY(1000*err); /* Returns expected delay in ms */
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if (err < 0) {
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device_printf(dev, "PHB reset poll failed: %d\n", err);
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return (ENXIO);
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}
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DELAY(10000);
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err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 0);
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if (err < 0) {
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device_printf(dev, "PHB reset completion failed: %d\n", err);
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return (ENXIO);
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}
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while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0)
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DELAY(1000*err); /* Returns expected delay in ms */
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if (err < 0) {
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device_printf(dev, "PHB reset completion poll failed: %d\n",
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err);
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return (ENXIO);
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}
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DELAY(10000);
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#endif
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/*
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* Map all devices on the bus to partitionable endpoint one until
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* such time as we start wanting to do things like bhyve.
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@ -282,6 +277,8 @@ opalpci_attach(device_t dev)
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/* XXX: multiple M64 windows? */
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if (OF_getencprop(ofw_bus_get_node(dev), "ibm,opal-m64-window",
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m64window, sizeof(m64window)) == sizeof(m64window)) {
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opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id,
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OPAL_M64_WINDOW_TYPE, 0, 0);
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opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, sc->phb_id,
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OPAL_M64_WINDOW_TYPE, 0 /* index */,
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((uint64_t)m64window[2] << 32) | m64window[3], 0,
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@ -294,20 +291,53 @@ opalpci_attach(device_t dev)
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}
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/*
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* Also disable the IOMMU for the time being for PE 1 (everything)
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* Enable IOMMU for PE1 - map everything 1:1 using
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* segments of OPAL_PCI_TCE_SEG_SIZE size
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*/
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maxmem = roundup2(powerpc_ptob(Maxmem), OPAL_PCI_TCE_SEG_SIZE);
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entries = maxmem / OPAL_PCI_TCE_SEG_SIZE;
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if (entries > OPAL_PCI_TCE_MAX_ENTRIES)
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panic("POWERNV supports only %jdGB of memory space\n",
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(uintmax_t)((OPAL_PCI_TCE_MAX_ENTRIES * OPAL_PCI_TCE_SEG_SIZE) >> 30));
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if (bootverbose)
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device_printf(dev, "Mapping 0-%#lx for DMA\n",
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roundup2(powerpc_ptob(Maxmem), 16*1024*1024));
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err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id,
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OPAL_PCI_DEFAULT_PE, OPAL_PCI_DEFAULT_PE << 1,
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0 /* start address */, roundup2(powerpc_ptob(Maxmem),
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16*1024*1024)/* all RAM */);
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if (err != 0) {
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device_printf(dev, "DMA mapping failed: %d\n", err);
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return (ENXIO);
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device_printf(dev, "Mapping 0-%#jx for DMA\n", (uintmax_t)maxmem);
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sc->tce = contigmalloc(OPAL_PCI_TCE_MAX_ENTRIES * sizeof(uint64_t),
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M_DEVBUF, M_NOWAIT | M_ZERO, 0,
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BUS_SPACE_MAXADDR_32BIT, OPAL_PCI_TCE_SEG_SIZE, 0);
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if (sc->tce == NULL)
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panic("Failed to allocate TCE memory for PHB %jd\n",
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(uintmax_t)sc->phb_id);
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for (i = 0; i < entries; i++)
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sc->tce[i] = (i * OPAL_PCI_TCE_SEG_SIZE) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W;
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/* Map TCE for every PE. It seems necessary for Power8 */
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for (i = 0; i < npe; i++) {
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err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, sc->phb_id,
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i, (i << 1),
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1, pmap_kextract((uint64_t)&sc->tce[0]),
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OPAL_PCI_TCE_MAX_ENTRIES * sizeof(uint64_t), OPAL_PCI_TCE_SEG_SIZE);
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if (err != 0) {
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device_printf(dev, "DMA IOMMU mapping failed: %d\n", err);
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return (ENXIO);
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}
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err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id,
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i, (i << 1) + 1,
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(1UL << 59), maxmem);
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if (err != 0) {
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device_printf(dev, "DMA 64b bypass mapping failed: %d\n", err);
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return (ENXIO);
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}
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}
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/*
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* Invalidate all previous TCE entries.
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*
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* TODO: add support for other PHBs than PHB3
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*/
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pci_phb3_tce_invalidate_entire(sc);
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/*
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* Get MSI properties
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*/
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@ -457,6 +487,7 @@ opalpci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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static int
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opalpci_route_interrupt(device_t bus, device_t dev, int pin)
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{
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return (pin);
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}
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