Implement a prototype interface to bus-master IDE DMA on the Triton
chipset. This does not attempt to do anything special with the timing on the hope that the BIOS will have done the right thing already. The actual interface from the wd driver to the new facility is not implemented yet (this commit being an attempt at prodding someone else to do it because looking at the wd driver always confuses the h*** out of me).
This commit is contained in:
Garrett Wollman
parent
93f4df92ad
commit
5dec5a0060
@ -1,7 +1,7 @@
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# This file tells config what files go into building a kernel,
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# files marked standard are always included.
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#
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# $Id: files.i386,v 1.124 1996/01/15 10:28:14 phk Exp $
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# $Id: files.i386,v 1.125 1996/01/24 18:47:58 peter Exp $
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#
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aic7xxx_asm optional ahc device-driver \
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dependency "$S/dev/aic7xxx/aic7xxx_asm.c" \
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@ -247,3 +247,4 @@ gnu/i386/fpemul/wm_sqrt.s optional gpl_math_emulate
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gnu/i386/isa/dgb.c optional dgb device-driver
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gnu/i386/isa/nic3008.c optional nic device-driver
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gnu/i386/isa/nic3009.c optional nnic device-driver
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pci/wd82371.c optional wd device-driver
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@ -1,7 +1,7 @@
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# This file tells config what files go into building a kernel,
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# files marked standard are always included.
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#
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# $Id: files.i386,v 1.124 1996/01/15 10:28:14 phk Exp $
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# $Id: files.i386,v 1.125 1996/01/24 18:47:58 peter Exp $
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#
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aic7xxx_asm optional ahc device-driver \
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dependency "$S/dev/aic7xxx/aic7xxx_asm.c" \
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@ -247,3 +247,4 @@ gnu/i386/fpemul/wm_sqrt.s optional gpl_math_emulate
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gnu/i386/isa/dgb.c optional dgb device-driver
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gnu/i386/isa/nic3008.c optional nic device-driver
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gnu/i386/isa/nic3009.c optional nnic device-driver
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pci/wd82371.c optional wd device-driver
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)wd.c 7.2 (Berkeley) 5/9/91
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* $Id: wd.c,v 1.102 1996/01/16 18:13:16 phk Exp $
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* $Id: wd.c,v 1.103 1996/01/27 04:17:52 bde Exp $
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*/
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/* TODO:
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@ -269,6 +269,8 @@ static struct {
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int b_active;
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} wdtab[NWDC];
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struct wddma wddma;
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#ifdef notyet
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static struct buf rwdbuf[NWD]; /* buffers for raw IO */
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#endif
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)wdreg.h 7.1 (Berkeley) 5/9/91
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* $Id: wdreg.h,v 1.9 1995/11/04 13:23:45 bde Exp $
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* $Id: wdreg.h,v 1.10 1995/11/04 17:07:58 bde Exp $
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*/
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/*
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@ -142,4 +142,49 @@ struct wdparams {
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int wdformat(struct buf *bp);
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#endif
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/*
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* IDE DMA support.
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* This is based on what is needed for the IDE DMA function of the Intel
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* Triton chipset; hopefully it's general enough to be used for other
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* chipsets as well.
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*
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* To use this:
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* For each drive which you might want to do DMA on, call wdd_candma()
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* to get a cookie. If it returns a null pointer, then the drive
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* can't do DMA.
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*
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* Set up the transfer be calling wdd_dmaprep(). The cookie is what
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* you got before; vaddr is the virtual address of the buffer to be
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* written; len is the length of the buffer; and direction is either
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* B_READ or B_WRITE.
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*
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* Send a read/write DMA command to the drive.
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*
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* Call wdd_dmastart().
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*
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* Wait for an interrupt. Multi-sector transfers will only interrupt
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* at the end of the transfer.
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*
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* Call wdd_dmadone(). It will return the status as defined by the
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* WDDS_* constants below.
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*/
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struct wddma {
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void *(*wdd_candma) /* returns a cookie if can do DMA */
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__P((int ctlr, int drive));
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int (*wdd_dmaprep) /* prepare DMA hardware */
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__P((void *cookie, char *vaddr, u_long len, int direction));
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void (*wdd_dmastart) /* begin DMA transfer */
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__P((void *cookie));
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int (*wdd_dmadone) /* DMA transfer completed */
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__P((void *cookie));
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int (*wdd_dmastatus) /* return status of DMA */
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__P((void *cookie));
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};
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#define WDDS_ACTIVE 0x0001
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#define WDDS_ERROR 0x0002
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#define WDDS_INTERRUPT 0x0004
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extern struct wddma wddma;
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#endif /* KERNEL */
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@ -1,6 +1,6 @@
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/**************************************************************************
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**
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** $Id: pcisupport.c,v 1.29 1996/01/25 20:38:31 wollman Exp $
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** $Id: pcisupport.c,v 1.30 1996/01/27 20:14:32 wollman Exp $
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**
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** Device driver for DEC/INTEL PCI chipsets.
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**
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@ -107,8 +107,6 @@ chipset_probe (pcici_t tag, pcidi_t type)
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return ("Intel 82437 (Triton) PCI cache memory controller");
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case 0x122e8086:
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return ("Intel 82371 (Triton) PCI-ISA bridge");
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case 0x12308086:
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return ("Intel 82371 (Triton) Bus-master IDE controller");
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case 0x04961039:
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return ("SiS 85c496");
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case 0x04061039:
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@ -501,6 +499,7 @@ static const struct condmsg conf82371fb[] =
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{ 0 }
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};
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#if 0 /* xxx not used */
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static const struct condmsg conf82371fb2[] =
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{
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/* IDETM -- IDE Timing Register */
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@ -513,6 +512,7 @@ static const struct condmsg conf82371fb2[] =
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/* end of list */
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{ 0 }
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};
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#endif
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static char confread (pcici_t config_id, int port)
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{
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@ -587,11 +587,11 @@ chipset_attach (pcici_t config_id, int unit)
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case 0x122e8086:
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writeconfig (config_id, conf82371fb);
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break;
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#if 0
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case 0x12308086:
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printf("\tI/O Base Address: %#lx\n",
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(u_long)pci_conf_read(config_id, 0x20) & 0xfff0);
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writeconfig (config_id, conf82371fb2);
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break;
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#endif
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};
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#endif /* PCI_QUIET */
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}
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308
sys/pci/wd82371.c
Normal file
308
sys/pci/wd82371.c
Normal file
@ -0,0 +1,308 @@
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/*
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* Copyright 1996 Massachusetts Institute of Technology
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby
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* granted, provided that both the above copyright notice and this
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* permission notice appear in all copies, that both the above
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* copyright notice and this permission notice appear in all
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* supporting documentation, and that the name of M.I.T. not be used
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* in advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission. M.I.T. makes
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* no representations about the suitability of this software for any
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* purpose. It is provided "as is" without express or implied
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* warranty.
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*
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* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
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* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
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* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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#include "pci.h"
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#if NPCI > 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/queue.h>
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#include <sys/proc.h>
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#include <sys/buf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/pmap.h> /* for vtophys */
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#include <i386/isa/wdreg.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <pci/wd82371reg.h>
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static void *piix_candma(int, int);
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static int piix_dmasetup(void *, char *, u_long, int);
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static void piix_dmastart(void *);
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static int piix_dmadone(void *);
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static int piix_status(void *);
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struct piix_cookie {
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LIST_ENTRY(piix_cookie) le;
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int ctlr;
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int unit;
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struct piix_prd *prd;
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};
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struct piix_softc {
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unsigned iobase;
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pcici_t tag;
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LIST_HEAD(, piix_cookie) cookies;
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};
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static struct piix_softc softc;
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static struct piix_cookie *
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mkcookie(int ctlr, int unit)
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{
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struct piix_cookie *cp;
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cp = malloc(sizeof *cp, M_DEVBUF, M_NOWAIT);
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if (!cp) return cp;
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cp->ctlr = ctlr;
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cp->unit = unit;
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cp->prd = malloc(PRD_ALLOC_SIZE, M_DEVBUF, M_NOWAIT);
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if (!cp->prd) {
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FREE(cp, M_DEVBUF);
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return 0;
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}
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LIST_INSERT_HEAD(&softc.cookies, cp, le);
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return cp;
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}
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static char *
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piix_probe(pcici_t tag, pcidi_t type)
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{
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if (type == 0x12308086)
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return ("Intel 82371 (Triton) Bus-master IDE controller");
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return 0;
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}
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static void
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piix_attach(pcici_t tag, int unit)
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{
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u_long idetm;
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int bmista;
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int iobase;
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if (unit) return;
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softc.tag = tag;
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iobase = softc.iobase = pci_conf_read(tag, 0x20) & 0xfff0;
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idetm = pci_conf_read(tag, 0x40);
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LIST_INIT(&softc.cookies);
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if (IDETM_CTLR_0(idetm) & IDETM_ENABLE) {
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bmista = inb(iobase + BMISTA_PORT);
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if (bmista & BMISTA_DMA0CAP)
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mkcookie(0, 0);
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if (bmista & BMISTA_DMA1CAP)
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mkcookie(0, 1);
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}
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if (IDETM_CTLR_1(idetm) & IDETM_ENABLE) {
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bmista = inb(iobase + PIIX_CTLR_1 + BMISTA_PORT);
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if (bmista & BMISTA_DMA0CAP)
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mkcookie(1, 0);
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if (bmista & BMISTA_DMA1CAP)
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mkcookie(1, 1);
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}
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wddma.wdd_candma = piix_candma;
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wddma.wdd_dmaprep = piix_dmasetup;
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wddma.wdd_dmastart = piix_dmastart;
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wddma.wdd_dmadone = piix_dmadone;
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wddma.wdd_dmastatus = piix_status;
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}
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static u_long piix_count;
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static struct pci_device piix_device = {
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"piix",
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piix_probe,
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piix_attach,
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&piix_count,
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0
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};
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DATA_SET(pcidevice_set, piix_device);
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/*
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* Return a cookie if we can do DMA on the specified (ctlr, unit).
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*/
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static void *
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piix_candma(int ctlr, int unit)
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{
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struct piix_cookie *cp;
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cp = softc.cookies.lh_first;
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while(cp) {
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if (cp->unit == unit && cp->ctlr == ctlr)
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break;
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cp = cp->le.le_next;
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}
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return cp;
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}
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/*
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* Set up DMA for cp. It is the responsibility of the caller
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* to ensure that the controller is idle before this routine
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* is called.
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*/
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static int
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piix_dmasetup(void *xcp, char *vaddr, u_long count, int dir)
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{
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struct piix_cookie *cp = xcp;
|
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struct piix_prd *prd;
|
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int i;
|
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u_long pgresid;
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int iobase;
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|
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prd = cp->prd;
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i = 0;
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iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
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/*
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* Deal with transfers that don't start on a page
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* boundary.
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*/
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pgresid = (u_long)vaddr & ~NBPG;
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if (pgresid) {
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prd[i].prd_base = vtophys(vaddr);
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if (count >= (NBPG - pgresid))
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prd[i].prd_count = NBPG - pgresid;
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else
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prd[i].prd_count = count;
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vaddr += prd[i].prd_count;
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count -= prd[i].prd_count;
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prd[i].prd_eot |= PRD_EOT_BIT;
|
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i++;
|
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}
|
||||
|
||||
/*
|
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* We have now ensured that vaddr is page-aligned, so just
|
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* step through the pages adding each one onto the list.
|
||||
*/
|
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while(count) {
|
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u_long phys, n;
|
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|
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phys = vtophys(vaddr);
|
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n = (count > NBPG) ? NBPG : count;
|
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/*
|
||||
* If the current page is physically contiguous with
|
||||
* whatever we have in the previous PRD, just tack it
|
||||
* onto the end.
|
||||
* CAVEAT: due to a hardware deficiency, PRDs
|
||||
* cannot cross a 64K boundary.
|
||||
*/
|
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if (i > 0
|
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&& phys == prd[i - 1].prd_base + prd[i - 1].prd_count
|
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&& ((prd[i - 1].prd_base & 0xffff)
|
||||
+ prd[i - 1].prd_count + n) <= 65535) {
|
||||
|
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prd[i - 1].prd_count += n;
|
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} else {
|
||||
if (i > 0)
|
||||
prd[i - 1].prd_eot &= ~PRD_EOT_BIT;
|
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prd[i].prd_base = phys;
|
||||
prd[i].prd_count = n;
|
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prd[i].prd_eot |= PRD_EOT_BIT;
|
||||
i++;
|
||||
if (i >= PRD_MAX_SEGS)
|
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panic("wd82371: too many segments\n");
|
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}
|
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count -= n;
|
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vaddr += n;
|
||||
}
|
||||
|
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/* Set up PRD base register */
|
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outl(iobase + BMIDTP_PORT, vtophys(prd));
|
||||
|
||||
/* Set direction of transfer */
|
||||
if (dir == B_READ) {
|
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outb(iobase + BMICOM_PORT, 0);
|
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} else {
|
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outb(iobase + BMICOM_PORT, BMICOM_READ_WRITE);
|
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}
|
||||
|
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/* Clear interrupt and error bits */
|
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outb(iobase + BMISTA_PORT,
|
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(inb(iobase + BMISTA_PORT)
|
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& ~(BMISTA_INTERRUPT | BMISTA_DMA_ERROR)));
|
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|
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return 0;
|
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}
|
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|
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static void
|
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piix_dmastart(void *xcp)
|
||||
{
|
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struct piix_cookie *cp = xcp;
|
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int iobase;
|
||||
|
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iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
|
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|
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outb(iobase + BMICOM_PORT,
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inb(iobase + BMICOM_PORT) | BMICOM_STOP_START);
|
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}
|
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|
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static int
|
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piix_dmadone(void *xcp)
|
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{
|
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struct piix_cookie *cp = xcp;
|
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int iobase, status;
|
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|
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status = piix_status(xcp);
|
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iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
|
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|
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outb(iobase + BMICOM_PORT,
|
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inb(iobase + BMICOM_PORT) & ~BMICOM_STOP_START);
|
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|
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return status;
|
||||
}
|
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|
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static int
|
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piix_status(void *xcp)
|
||||
{
|
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struct piix_cookie *cp = xcp;
|
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int iobase, status, bmista;
|
||||
|
||||
status = 0;
|
||||
iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
|
||||
|
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bmista = inb(iobase + BMISTA_PORT);
|
||||
|
||||
if (bmista & BMISTA_INTERRUPT)
|
||||
status |= WDDS_INTERRUPT;
|
||||
if (bmista & BMISTA_DMA_ERROR)
|
||||
status |= WDDS_ERROR;
|
||||
if (bmista & BMISTA_DMA_ACTIVE)
|
||||
status |= WDDS_ACTIVE;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* NPCI > 0 */
|
||||
80
sys/pci/wd82371reg.h
Normal file
80
sys/pci/wd82371reg.h
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright 1996 Massachusetts Institute of Technology
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software and
|
||||
* its documentation for any purpose and without fee is hereby
|
||||
* granted, provided that both the above copyright notice and this
|
||||
* permission notice appear in all copies, that both the above
|
||||
* copyright notice and this permission notice appear in all
|
||||
* supporting documentation, and that the name of M.I.T. not be used
|
||||
* in advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission. M.I.T. makes
|
||||
* no representations about the suitability of this software for any
|
||||
* purpose. It is provided "as is" without express or implied
|
||||
* warranty.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
|
||||
* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
|
||||
* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _PCI_WD82371REG_H_
|
||||
#define _PCI_WD82371REG_H_ 1
|
||||
|
||||
/* Contents of IDETM register, as two 16-bit words (high ctlr 1, low ctlr 0) */
|
||||
#define IDETM_ENABLE 0x8000
|
||||
#define IDETM_IORDY_SAMP 0x3000 /* 00:5, 01:4, 10:3, 11:2 clocks */
|
||||
#define IDETM_RECOVERY_TIME 0x0300 /* 00:4, 01:3, 10:2, 11:1 clocks */
|
||||
#define IDETM_TIMING_ENB_1 0x0080
|
||||
#define IDETM_PREFETCH_POST_1 0x0040
|
||||
#define IDETM_ISP_ENB_1 0x0020 /* enabled IORDY sampling */
|
||||
#define IDETM_FAST_TIMING_1 0x0010
|
||||
#define IDETM_TIMING_ENB_0 0x0008
|
||||
#define IDETM_PREFETCH_POST_0 0x0004
|
||||
#define IDETM_ISP_ENB_0 0x0002
|
||||
#define IDETM_FAST_TIMING_0 0x0001
|
||||
|
||||
#define IDETM_CTLR_0(x) (x)
|
||||
#define IDETM_CTLR_1(x) ((x) >> 16)
|
||||
|
||||
/* Ports are for controller 0. Add PIIX_CTLR_1 for controller 1. */
|
||||
#define PIIX_CTLR_1 8
|
||||
|
||||
/* Contents of BMICOM register */
|
||||
#define BMICOM_PORT 0
|
||||
#define BMICOM_READ_WRITE 0x0008 /* false = read, true = write */
|
||||
#define BMICOM_STOP_START 0x0001 /* false = stop, true = start */
|
||||
|
||||
/* Contents of BMISTA register */
|
||||
#define BMISTA_PORT 2
|
||||
#define BMISTA_DMA1CAP 0x0040 /* true = drive 1 can DMA */
|
||||
#define BMISTA_DMA0CAP 0x0020 /* true = drive 0 can DMA */
|
||||
#define BMISTA_INTERRUPT 0x0004
|
||||
#define BMISTA_DMA_ERROR 0x0002
|
||||
#define BMISTA_DMA_ACTIVE 0x0001
|
||||
|
||||
#define BMIDTP_PORT 4 /* use outl */
|
||||
|
||||
struct piix_prd {
|
||||
u_int32_t prd_base;
|
||||
u_int16_t prd_eot;
|
||||
u_int16_t prd_count;
|
||||
};
|
||||
|
||||
#define PRD_EOT_BIT 0x8000
|
||||
|
||||
#define PRD_ALLOC_SIZE 4096
|
||||
#define PRD_MAX_SEGS (PRD_ALLOC_SIZE / 4)
|
||||
|
||||
#endif /* _PCI_WD82371REG_H_ */
|
||||
Loading…
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Reference in New Issue
Block a user