Comments and style(9) only, no functional changes.
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7815365774
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@ -158,34 +158,33 @@ bus_dma_get_range_nb(void)
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return (0);
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}
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/*
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* This code which manipulates the watchdog hardware is here to implement
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* cpu_reset() because the watchdog is the only way for software to reset the
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* chip. Why here and not in imx_wdog.c? Because there's no requirement that
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* the watchdog driver be compiled in, but it's nice to be able to reboot even
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* if it's not.
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*/
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void
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imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr)
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{
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const struct pmap_devmap *pd;
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volatile uint16_t * pcr;
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/*
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* This code which manipulates the watchdog hardware is here to
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* implement cpu_reset() because the watchdog is the only way for
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* software to reset the chip. Why here and not in imx_wdog.c? Because
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* there's no requirement that the watchdog driver be compiled in, but
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* it's nice to be able to reboot even if it's not.
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* The deceptively simple write of WDOG_CR_WDE enables the watchdog,
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* sets the timeout to its minimum value (half a second), and also
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* clears the SRS bit which results in the SFTW (software-requested
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* reset) bit being set in the watchdog status register after the reset.
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* This is how software can distinguish a reset from a wdog timeout.
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*/
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volatile uint16_t * pcr;
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const struct pmap_devmap *pd;
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if ((pd = pmap_devmap_find_pa(wdcr_physaddr, 2)) == NULL) {
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printf("cpu_reset() can't find its control register... locking up now.");
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} else {
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pcr = (uint16_t *)(pd->pd_va + (wdcr_physaddr - pd->pd_pa));
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/*
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* This deceptively simple write enables the watchdog, sets the timeout
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* to its minimum value (half a second), and also clears the SRS bit
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* which results in the SFTW (software-requested reset) bit being set in
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* the watchdog status register after the reset. This is how software
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* can distinguish a requested reset from a wdog timeout.
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*/
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*pcr = WDOG_CR_WDE;
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}
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while (1)
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for (;;)
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continue;
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}
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